Good to know. I have a paper here from Bell Labs that shows the difference between the Gummel-Poon model and real measurements. There is more difference that I would have thought.
Now, just to be clear: The drive impedance for the output stage is 1gig-Ohm or more? (at low frequencies)
Now, just to be clear: The drive impedance for the output stage is 1gig-Ohm or more? (at low frequencies)
scott wurcer said:
Hmm, sounds a bit suspicious. I've seen this before with models that have a too-high RC when simulated at a small VCB. What I've seen happen is that even though the external VCB may be constant, the intrinsic VCB is decreasing as IC increases, because of RC. Then the Early effect comes into play, very gradually reducing simulated beta as IC increases. The OnSemi MJL3281A model had this problem. Same "no beta peak" symptom.
What value of VCB did you use? It might be good to try, say, 14 Volts. Also, were your models as good back then as they are now? I've seen RC sometimes used to "fake" quasi-sat. In fact, Massobrio and Antognetti recommend this. It was written before models with quasi-sat parameters were widely available. I disagree with their recommendation and always used RC to only model hard sat. This gives a much smaller RC value.
andy_c said:
It's pretty typical for an old-ish IC process. Reason is carrier recombination in the buried layer. The phenomenon is even worse for lateral pnp's.
The buried layer design is a trade off between small collector series resistence and carrier recombination leading to beta drop.
Just another example of why extrapolating discrete devices knowledge to integrated devices is not always productive.
andy_c said:
I tried 10V and keeping Vcb constant. It was a little better at 10V. The models are no better than primitive old SPICE models, actually standard test devices were run and measured and fit to theory. This sometimes gave nonsense values for things like rbb for instance (nothing measured was sensitive to it so it becomes an independent fitting parameter with no limits on variance).
This process is officially unsupported now. We actually have a process guy that wrote some of the stuff in Sze (a bible) but I can't justify using his time for this.
Here you go again John, I'm eager to please and want to be helpful. This is the total current load of the output stage with 10k load (the feedback network) and an extra 600 Ohms (the rated load). I was pretty close with my guess its about 600Meg and 200 Meg worst case.
It appears the thumbnailer has an issue with transparent gifs?
It appears the thumbnailer has an issue with transparent gifs?
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scott wurcer said:
No problemo. I wasn't trying to bust your chops here - I was just curious because I've only seen this "beta tilt" thing in simulation and not in any device datasheet. But then again, I don't have the familiarity with the kind of things specific to IC processes that syn08 has mentioned either.
Also, I should correct my earlier post. I should have said "no beta plateau" instead of "no beta peak".
It sounds to me like the modeling efforts at ADI have come a long way since then.
G.Kleinschmidt said:
Well that sure ain't Wilbur.
I was just clairifying there Andy, trying to help out JC. As the saying goes, "You can lead them to the "fountain""....
G.Kleinschmidt said:
No, it's Clever Hans doing a DBT 🙂.
The story of Clever Hans is great fun to read and reminds me of audiophilia.
scott wurcer said:
Oh I was just wondering about the horse. There was a science program on the ABC a while ago with a segment on horse training.
The scientists ran a series of tests and they found that a horse is about as bright as a gold fish.
If Clever Hans was alive today he could chief audio tester for Stereophile.
G.Kleinschmidt said:
Before the bubble there was a student funded at the Media Lab at MIT trying to make fish more "engaging" pets. I kid you not.
Scott, is that the real numbering of devices?
If yes, it is visible how VAS turned into a diode when that new super-VAS was added in between, then that "limiter" to it, how levels were shifted later, and so on... 😎
Edit: it's like a history of starting from a round horse in vacuum 😎
If yes, it is visible how VAS turned into a diode when that new super-VAS was added in between, then that "limiter" to it, how levels were shifted later, and so on... 😎
Edit: it's like a history of starting from a round horse in vacuum 😎
Gee Scott, I thought it was 'perfect linearity forever'
😀
Looks better than some IC's that I measured open loop in '74 with the Tektronix box, but somewhat worse than the original JC-2 line stage, open loop.
Of course, that has been my concern, all along.
😀
Looks better than some IC's that I measured open loop in '74 with the Tektronix box, but somewhat worse than the original JC-2 line stage, open loop.
Of course, that has been my concern, all along.
"Everything is **** except bees. Though, bees are **** as well" -- do you remember that Russian saying I taught you? 😉
Pulling teeth again, I guess there's no point. This is not the open loop gain it's the current demand of the output stage. So let's see 30nA in a gm of 1/50 Ohms, that's 1.5uV (Aol = ~6Meg) with a few nV of non -linearity. Never measurable on the Tek op-amp curve tracer (what a shame they tossed ours). Talk about synchronicity, I just scavenged the socket assemblies from today's trash.
john curl said:Cut the small talk, Wavebourn. I have little or no idea what you are talking about.
Let me remind you: it is about optimization that is the twin-sister in any design and engineering, because nothing is perfect. You can't build absolutely the best thing using absolutely best components: there are no such things in the real world. If you want to use an opamp to cut costs and sizes you should know it's character, what you trade off for size and cost. If you want to build something different to optimize by different parameters you can do something better, but in terms of parameters you optimize for primarily, trading off another parameters that are weighted less in an optimization equation.
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