If a first order, low pass amplifier has significantly greater bandwidth than the signal,
then the amplifier's effective time delay is approximately = -1/BW, where the
bandwidth BW is in Hz. This was at one time termed "integrator delay".
This is because the amplifier's phase shift is -arctan (f/BW), and is approximately linear
for f much less than the BW, where -arctan (f/BW) ~ -f/BW. Then this linear phase is
equivalent to a time delay of -1/BW, since d(phase)/df = d/df (-f/BW) = -1/BW.
This is distinct from propagation delay, and is unrelated to it.
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It probably takes long time delays on the order of a second or even more to do that. That can get costly and the delay may not be compatible with some applications like video playback, video editing, DAW editing, etc. At some price point for a really good dac there could be a high quality, long delay mode, and a lower sound quality, short delay mode. IIRC, Chord Dave has that, but it also costs maybe 6 times as much as DAC-3. Stereophile is probably correct in classifying DAC-3 price as a bargain.
Also, IMHO, what constitutes and 'top SOTA dac' changes maybe every decade or so. DAC-1 was considered that at one time, but not anymore. The era of DAC-3 may be about to change with the arrival AKM's new chip and with more dac designs making better use of DSP. I am watching with interest to see what happens.
That rules out SPDIF, TOSLINK, and AES. Only leaves USB, and RPi music players. What if someone wants to bi-amp a surround system? Are they going to have a USB interface to every dac in the system and have the whole thing stay in sync? How about upsample the whole music library to DSD512, and pre-electronic crossover and apply room correction in advance into files ready to play for each of the dacs?
General purpose microprocessors that run desktop operating systems, have had full 64 bit internal registers, internal datapaths, and external datapaths, since 1990. In the subsequant 29 years, lithographic featuresize has shrunk from 800 nanometers to 10 nanometers. FPGAs with millions of gate equivalents and hundreds of I/Os have become commonplace ... clocked at more than a gigahertz.
Anybody who wants a DSP with a wide wide datapath to ensure big big overload margin, merely has to sit down and type it up in Verilog. Whoosh, it goes straight to FPGA where it runs at hardware (not software) speeds, all day long. Want 120 bit datapaths? You got it.
Anybody who wants a DSP with a wide wide datapath to ensure big big overload margin, merely has to sit down and type it up in Verilog. Whoosh, it goes straight to FPGA where it runs at hardware (not software) speeds, all day long. Want 120 bit datapaths? You got it.
You don't need sample rate conversion to use SPDIF or other interfaces that carry the master clock. You can just use the recovered master clock - the new receivers like DIX4192, WM880x, etc. have relatively low amounts of jitter - or you can use your own PLL or FIFO + VCO.
I will admit that an ASRC is attractive for SPDIF inputs.
AES67 sounds like a better solution to a multichannel issue.
Upsampling a library to DSD512 is not a good thing either, but since you like it, continue I guess.
Well, you can complicate things needlessly if you want.
I'm only interested in playing my ripped music. It's all at same SR, system is biamped, dsp controlled, optically linked, no problems.
Still wonder why you have no measurements of problems with reverb?
Well, I dont really care so wouldnt look further.
Since I dont know you, i would have to leave an open mind about what you said .... would not accept it, necessarily. Only if I researched it, as you thought i might, would I take a side.
THx-RNMarsh
Feedback, in the context of an analog amplifier, is not recursive. The signal does not go through the amplifier get distorted a little and go back through again and get distorted some more and on and on as is implied.
I didn't say I was doing it, AK4137 can't even do DSD512. I was speaking of people doing it with their TP dacs, etc., using apps like HQPlayer, Roon, etc. People seem to think it sounds better, is why.
To save anyone from having to wonder, its not high on my priority list. Doing it won't particularly help with any end purpose I would like to get accomplished. I already have sufficient reason to continue trying to reduce jitter a little bit more if I can, and to continue learning about FPGA programming and programming the newer Sharc chips. There are trade offs with different features, chip prices, software licensing, etc. Lots to think about.
OK, so everyone has been wasting their time, that is what this thread seems to be for....ho-hum
It may have been a demonstration of the first point. We do not bother to measure everything that is audible. Do you want to measure it?
If you apply a signal in one input and look at the associated feedback node you will see that it shows a non-zero value immediately, aside from any relativistic delays. The feedback signal will peak later than the input signal due to the phase shift through the system but there is point anywhere where the feedback signal does not relate directly to the input signal when operating in its linear region.
If its 'delay' (and not phase shift) related to 1/BW, then on a 100kHz input stimulus there would be a 10 second 'delay' around the loop and the amplifier would be running 'open loop'. An amplifier running open loop for 10us does not work - its the old chestnut rolled out by Colloms et al
But, better than that, it can be tried out on LTspice.
To quote Floyd Toole: (regularly trotted out by planet10)
Two ears and a brain are massively more analytical and adaptable than an omnidirectional microphone and an analyzer.
So what's the point?
The Auralic Vega has four clock PLL settings which are user adjustable: Auto/ Coarse/Fine/Exact, which have the same characteristic you state. In the Exact mode if there is any input jitter or uneven latency (long T jitter...) it will insert pauses, letting you know the source is unstable. I feed the Vega with a high-end Asus motherboard USB3 and can usually keep it on Exact, but with some sources, especially streaming have to back it down to Fine, or if I am switching sources a lot leave it at Auto.
Cheers,
Howie
If you're designing an 8x interpolation filter or whatever, you can certainly do the math in a DSP like the SHARC but most DSPs are limited to 192 KHz on the I2S peripherals. That's one reason why you see most external filters done in the FPGAs.
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