Hi, I'd like to thank you guys for your guidance on the problem I had with the DC offset.
As per my previous post, it appeared that the problem was the difference in gain between the P channel LTPs and the N channel LTPs.
I ordered a quantity of 546 and 556 transistors and gain matched 4 transistors. I also bonded them together to help with thermal tracking.
The 2 NPNs and 2 PNPs were pretty much spot on, although I couldn't quite get a perfect match between P side and N side the 2 sides ended up about 8 out. The offset has now been reduced drastically to about 3mv.
I haven't yet had a chance to put them back together yet, but waveforms and all else seems fine. I've left them on soak test for a while to make sure they remain stable.
As per my previous post, it appeared that the problem was the difference in gain between the P channel LTPs and the N channel LTPs.
I ordered a quantity of 546 and 556 transistors and gain matched 4 transistors. I also bonded them together to help with thermal tracking.
The 2 NPNs and 2 PNPs were pretty much spot on, although I couldn't quite get a perfect match between P side and N side the 2 sides ended up about 8 out. The offset has now been reduced drastically to about 3mv.
I haven't yet had a chance to put them back together yet, but waveforms and all else seems fine. I've left them on soak test for a while to make sure they remain stable.
