A good review of SRPP operation is at The Tube CAD Journal,SRPP Decoded . Looking at the recent simulation, the resistor that does the work is R4. The gate resistors are stoppers. The SRPP really needs a fixed load to shine, and will be variable gain if confronted with a variable load like the passive RIAA network. This is pointed out very early in the thread with simulation results, and why I abandoned the SRPP for a while before coming up with the notion of a fixed load coupled with a large cap, and a folllower. THe Elektor SRPP circuit also loads the input SRPP stage with a fixed AC coupled resistor. All I did in the simulation was add symmetric cascode fets. These will be very necessary if the circuit is to be used as the input of a MM RIAA preamp - otherwise the amplified Miller capacitance would get out of hand. Simulating this cascode is easy - the practice is harder. I have a cascoded SRPP board sitting on my desk at work for the better part of a year now. I haven't given it a lot of attention, as there has been a lot of other low-hanging fruit (as well as work), but so far I have not been able to get the cascoded SRPP outputs to balance a ~1/2 VCC. For a non-cascoded SRPP, this is not too difficult to do, given careful selection of the jfets in question, and in deed, shorting out the cascode jfets allows proper centering. I think that the cascoded SRPP will also need careful selection of the cascode jfets so that each cascoded fet sees the same voltage. This is something I intend to find out this year - call it my New Year's resolution if you will.
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Can we say in your case that J5,J4 form a cascoded common source and J6,J3 form a cascoded common drain? In unison working as SRPP due to R5 connection?
That's pretty much the case. I had a chance to glance through the SRPP article I cited, and there are lots of nice tidbits and ideas for further research, including the skeleton of the circuit Papa Pass used for the output of one of his depletion-mode based First Watt amps. I really need to grab the VTV CDs if they are still available. There is always something thought-provoking to be found there.
I misspoke, it's Tube Cad I was looking for, and a lot of the articles are available at tubecad.com for download as PDFs - I've been busy clicking away...
Hello,
Back in the circuit in post 130 the output of The SRPP feeds the input of the follower/buffer stage. Seems that the SRPP would see close to constant load impedance and perform well.
I like the New Year’s resolution.
Thoughts regarding JFET selection:
How about a jig with resistors equal to R1 and R6 in place, plug in an assortment of JFET’s one at a time, measure and record. Then select JFET’s with equal current as tested in a bread board (test jig) with circuit values that match the circuit you will build? This does not test for Idss or any other single text book variable but the in circuit installed sum of variable interactions. Pick a current value that you like or fits the stock on hand.
I know, why don’t I do it? Just thoughts. I have not seen selection done this way. Seems like a practical approach
DT
Back in the circuit in post 130 the output of The SRPP feeds the input of the follower/buffer stage. Seems that the SRPP would see close to constant load impedance and perform well.
I like the New Year’s resolution.
Thoughts regarding JFET selection:
How about a jig with resistors equal to R1 and R6 in place, plug in an assortment of JFET’s one at a time, measure and record. Then select JFET’s with equal current as tested in a bread board (test jig) with circuit values that match the circuit you will build? This does not test for Idss or any other single text book variable but the in circuit installed sum of variable interactions. Pick a current value that you like or fits the stock on hand.
I know, why don’t I do it? Just thoughts. I have not seen selection done this way. Seems like a practical approach
DT
I set my fet tester to a given current (I would look at the middle of the range for a given IDSS grouping as a starter) and start measuring Vgs at that current, looking for close Vgs groupings. You have to work with what is available. Once you have some fets closely sorted for Vgs at a given drain current, then you can choose the source resistors. This is a more realistic way of sorting, as it allows you to work with what you are dealt from a given buy of jfets.
A hint - buy lots of jfets - it makes sorting easier, and you never know when your favorite jfet is going to be axed - they're dropping like flies...
Also, if you are serious about working with jfets, you need to come up with some sort of sorting jig.
A hint - buy lots of jfets - it makes sorting easier, and you never know when your favorite jfet is going to be axed - they're dropping like flies...
Also, if you are serious about working with jfets, you need to come up with some sort of sorting jig.
sorting jFETs by selecting Idss gets you a bunch of selected Idss jFETs.
That is not matching.
The extra steps described in posts147 & 148 are matching for other parameters than just Idss.
In my opinion the most important Pair of variables are Transconductance and Idss.
Selecting for both of these parameters give a pair of devices that when connected as a thermally coupled LTP will track each other for Id as Vgs is varied. Both the above methods are using a form of matching that is taking account of transconductance.
That is not matching.
The extra steps described in posts147 & 148 are matching for other parameters than just Idss.
In my opinion the most important Pair of variables are Transconductance and Idss.
Selecting for both of these parameters give a pair of devices that when connected as a thermally coupled LTP will track each other for Id as Vgs is varied. Both the above methods are using a form of matching that is taking account of transconductance.
Hello,
It is the New Year Andrew; you are 8 hours ahead of us.
Last year in weak moments I did buy a panel current meter and volt meter to make a JFET testing jig. I also bought a boat load (1000) of one JFET (2SK170 BL) because I could on Ebay. I think that I will sample the first 50 that comes out of the bag. In thinking about sorting, if I sort to the 9.9999 level of precession for 3 variables I may come up with 50 distinct piles of one. Or I could sort by a major variable then sub variables…. I will try several approaches with my sample of 50.
Since I have not seen it done this way I will start with the in circuit approach (post 147) and if there is a grouping around a current value I will take those JFETS and test/measure the Idss and the list of other suspects and see if there is a pattern that falls out.
This is all just for fun you know, not the best possible line stage or anything like that.
DT
It is the New Year Andrew; you are 8 hours ahead of us.
Last year in weak moments I did buy a panel current meter and volt meter to make a JFET testing jig. I also bought a boat load (1000) of one JFET (2SK170 BL) because I could on Ebay. I think that I will sample the first 50 that comes out of the bag. In thinking about sorting, if I sort to the 9.9999 level of precession for 3 variables I may come up with 50 distinct piles of one. Or I could sort by a major variable then sub variables…. I will try several approaches with my sample of 50.
Since I have not seen it done this way I will start with the in circuit approach (post 147) and if there is a grouping around a current value I will take those JFETS and test/measure the Idss and the list of other suspects and see if there is a pattern that falls out.
This is all just for fun you know, not the best possible line stage or anything like that.
DT
Andrew - nobody said a word about IDSS, not one. The tester I refer to has a variable current source and a jig to allow sorting Vgs vs. Id. For the SRPP circuit it appears essential to get a good Vgs match at your chosen operating current for proper output centering. Once you have the Vgs and Id, the source resistors follow (Ohm's law).
This is the fet sorting jig I currently use. It allows sorting jfets, and both depletion and enhancement mode mosfets. Current is continuously variable up to ~20 mA using a 10-turn precision pot. Two DVMs plug in via tip jacks for the measurements (reasonably good DVMs are much cheaper than panel meters, and you can use them elsewhere once you're done sorting). Though I put in a switch for testing IDSS, I've never used it.
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Wrench,
you don't understand your method.
I am not criticising you nor your method.
I am confirming that Id vs Vgs takes account of both transconductance and Idss.
If you get two devices that "match up" for Id @ set Vgs for three different Vgs (but equal between matches) then you have effectively defined a curve/line that shows the relation between Id and Vgs. That curve is an expression of Idss and transconductance.
If you want to check what I have just written then include Vgs= zero volts as one of the test curve values and you will see that the curve of both devices starts at Idss and slopes up through the first point and the second point.
Now take that same pair of matched devices and set Vgs such that you have the middle Vgs value giving the bias/quiescent current and select two Vgs values that give +10% Idq and -10% Idq. You will see again that these lie on that same curve that passes through Idss.
There are other parameters that will interfere with that matching, but I contend that if you get Idss and transconductance to match in the thermally coupled pair then the effect of variability in the other parameters is relatively minor.
you don't understand your method.
I am not criticising you nor your method.
I am confirming that Id vs Vgs takes account of both transconductance and Idss.
If you get two devices that "match up" for Id @ set Vgs for three different Vgs (but equal between matches) then you have effectively defined a curve/line that shows the relation between Id and Vgs. That curve is an expression of Idss and transconductance.
If you want to check what I have just written then include Vgs= zero volts as one of the test curve values and you will see that the curve of both devices starts at Idss and slopes up through the first point and the second point.
Now take that same pair of matched devices and set Vgs such that you have the middle Vgs value giving the bias/quiescent current and select two Vgs values that give +10% Idq and -10% Idq. You will see again that these lie on that same curve that passes through Idss.
There are other parameters that will interfere with that matching, but I contend that if you get Idss and transconductance to match in the thermally coupled pair then the effect of variability in the other parameters is relatively minor.
Maybe, but it's a lot easier to sort out pairs based on Vgs vs. Id. The gain matching between two sets of cascaded stages I've shown several times in this thread (even with an intervening RIAA network) shows that the technique suffices.
Andrew, I don't see why you insist on unnecessarily complicating the process of getting from a pile of fets to a finished SRPP gain cell. The method I have described has already resulted in 4 to 5 boards (most documented) here that have all had pretty close to the desired gain in each stage, and have matched very precisely left to right. Voltage centering in a given stage is also acceptable - indeed, this the first thing I measure when bringing up an SRPP stage to make sure that nothing has gone amiss.The only place where I have run into problems is the symmetric cascode, probably for the reasons I've enumerated already. It'll be interesting to see if I'm right.
Anyway, why don't you use the sorting method of your choice, make up a gain cell, and report the measurement results?
Anyway, why don't you use the sorting method of your choice, make up a gain cell, and report the measurement results?
I type this to understand not to any other purpose.
Back in post 143 you were speaking of selecting fets to obtain a desired voltage drop at the center of a series of 4 fets. This is the center position between two equal cascodes. I assume that there would also be a desired standard voltage drop between the top two fets and the bottom two fets as well. With you I am not discussing Idss or any other text book variable just Delta V.
A couple of other assumptions in my thinking: Each fet in the series chain will have equal current passing it. In the selection process for equal DC Delta V there is no AC signal included as part of the selection.
This stuff falls out of the assumptions: If all this is modeled in SPICE with perfectly identical fets and a perfect power supply we will know the idealized current through the series chain and the Delta V across each fet. Supply voltage, Resistors and other circuit parameters are selected to place operation on the sweet spot of the performance curve. (The SPICE model will include assigned values for the typical cast of text book variables)
I am seeing a different sort of test jig where the typical cast of text book variables will fall where they may. The fet under test will be placed in the test circuit created in the idealized spice circuit discussed above. The test voltage will be adjusted to the design Delta V and the current measured. Once all of the Delta V’s and currents match the model you have a pile selected fets.
Who knows where AC variables like in circuit gain and transconductance will fall or if they will be consistent among selected groups of 4 fets?
Comments please.
All Just for fun!
DT
Back in post 143 you were speaking of selecting fets to obtain a desired voltage drop at the center of a series of 4 fets. This is the center position between two equal cascodes. I assume that there would also be a desired standard voltage drop between the top two fets and the bottom two fets as well. With you I am not discussing Idss or any other text book variable just Delta V.
A couple of other assumptions in my thinking: Each fet in the series chain will have equal current passing it. In the selection process for equal DC Delta V there is no AC signal included as part of the selection.
This stuff falls out of the assumptions: If all this is modeled in SPICE with perfectly identical fets and a perfect power supply we will know the idealized current through the series chain and the Delta V across each fet. Supply voltage, Resistors and other circuit parameters are selected to place operation on the sweet spot of the performance curve. (The SPICE model will include assigned values for the typical cast of text book variables)
I am seeing a different sort of test jig where the typical cast of text book variables will fall where they may. The fet under test will be placed in the test circuit created in the idealized spice circuit discussed above. The test voltage will be adjusted to the design Delta V and the current measured. Once all of the Delta V’s and currents match the model you have a pile selected fets.
Who knows where AC variables like in circuit gain and transconductance will fall or if they will be consistent among selected groups of 4 fets?
Comments please.
All Just for fun!
DT
What I did with the cascode SRPP I currently have sitting around was to carefully select the Vgs vs. Id for the bottom fets, but not for the fets on top of the cascodes. This was a mistake, especially as the Id vs Vds characteristics aren't perfectly flat for the PN4393, less so than for devices with a longer channel.
When I get all my PN4391s together I need to yank out the 4391 cascode fets in my prototype and replace them with ones closely matched for Vgs at the Id of the bottom fets. If my reasoning is correct the stages should balance out better - after all , they center perfectly in the simulations, where all fets are precisely matched. I'll accept being within a volt or two of 1/2VCC, especially on the input stage, where the output amplitude is small. I'd want a little closer centering for the output stage, but that portion uses lower gm fets anyway.
I pick a drain current that generates good results in the simulation and then select at that current. This is relatively easy for me, as I have a jig where I can set the Id to anything I want up to ~20 mA. Unfortunately, you have to go with whatever matches fall out of your pile of fets, so the source resistors of the bottom fets may not exactly match what you have in the simulation.
I suppose you could also make a jig with the resistor of your choice in the source (don't forget a stopper resistor on the gate) and go with the Vgs values that match in that situation. In that case, your Id would be variable (though matching for the fets that match in Vgs), depending on what you have in your population of fets - hopefully not too terribly different than your desired design current. The PN4393s are problematic in that respect, as they have a wide range of specified IDSS. Parts that are binned more closely will be easier to select, like the 2SK30 - harder to get, but still a reasonable choice. There's an Ebay seller who is offering both the 2SK30 and 2SK117 in quantity. Both Salas and I have some of the 2SK30s - he thinks they may be legit.
As far as I can tell both methods posited here should yield good gain matching. Check the gain-phase plots I've posted so far for several prototypes in this thread. I also suspect that loading the SRPP cell the way I do makes for a more predictable gain.
I am going to try at some point to put together a gain cell using the 2SK117, first a simple SRPP so that I can see if I get get good voltage centering with something that simulates with such a high gain. If I succeed with that, then it will be time to try a cascode. It may be too touchy a circuit to be practical - I'll have to try it and see.
At any rate, I started this investigation to see if I could build a jfet SRPP. I was seduced by the excellent distortion predictions of the simulations, and frustrated by the failure of my first attempt using 2N5457s. So far the results sound ok, too, though I need more work on my system (especially on my speakers) to fully exploit any improvements in my phono chain. At any rate, I see no reason at this point to start waving any opamps around.
I also have 2-3 other phono preamp alternatives using single ended jfet designs lying about/in the works, including a gain cell I just posted tonight. It's hard to tell which one will win the sweepstakes. The jfet SRPP is something I'd never try for real mass production, but that doesn't matter a lot for DIY.
When I get all my PN4391s together I need to yank out the 4391 cascode fets in my prototype and replace them with ones closely matched for Vgs at the Id of the bottom fets. If my reasoning is correct the stages should balance out better - after all , they center perfectly in the simulations, where all fets are precisely matched. I'll accept being within a volt or two of 1/2VCC, especially on the input stage, where the output amplitude is small. I'd want a little closer centering for the output stage, but that portion uses lower gm fets anyway.
I pick a drain current that generates good results in the simulation and then select at that current. This is relatively easy for me, as I have a jig where I can set the Id to anything I want up to ~20 mA. Unfortunately, you have to go with whatever matches fall out of your pile of fets, so the source resistors of the bottom fets may not exactly match what you have in the simulation.
I suppose you could also make a jig with the resistor of your choice in the source (don't forget a stopper resistor on the gate) and go with the Vgs values that match in that situation. In that case, your Id would be variable (though matching for the fets that match in Vgs), depending on what you have in your population of fets - hopefully not too terribly different than your desired design current. The PN4393s are problematic in that respect, as they have a wide range of specified IDSS. Parts that are binned more closely will be easier to select, like the 2SK30 - harder to get, but still a reasonable choice. There's an Ebay seller who is offering both the 2SK30 and 2SK117 in quantity. Both Salas and I have some of the 2SK30s - he thinks they may be legit.
As far as I can tell both methods posited here should yield good gain matching. Check the gain-phase plots I've posted so far for several prototypes in this thread. I also suspect that loading the SRPP cell the way I do makes for a more predictable gain.
I am going to try at some point to put together a gain cell using the 2SK117, first a simple SRPP so that I can see if I get get good voltage centering with something that simulates with such a high gain. If I succeed with that, then it will be time to try a cascode. It may be too touchy a circuit to be practical - I'll have to try it and see.
At any rate, I started this investigation to see if I could build a jfet SRPP. I was seduced by the excellent distortion predictions of the simulations, and frustrated by the failure of my first attempt using 2N5457s. So far the results sound ok, too, though I need more work on my system (especially on my speakers) to fully exploit any improvements in my phono chain. At any rate, I see no reason at this point to start waving any opamps around.
I also have 2-3 other phono preamp alternatives using single ended jfet designs lying about/in the works, including a gain cell I just posted tonight. It's hard to tell which one will win the sweepstakes. The jfet SRPP is something I'd never try for real mass production, but that doesn't matter a lot for DIY.
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DT - by the way, I checked back a bit in the thread an saw that you have 2SK170s. I don't know exactly what you're trying to do, but they will give you a whole bunch of gain (probably too much) if used in an SRPP. Even the 2SK117, a humbler device in terms of gm, looks pretty slippery used that way. I suspect you'd have to load it heavily to bring the gain down, meaning a big load coupling cap. I'll try a sim some time in the next couple of days (I tried one before and was unimpressed). Maybe the intervening time will give me better insight, or maybe it'll be as problematic as last time. There are fortunately other ways of exploiting the goodness of a 2SK170.
I tried a sim for the 2SK170 in SRPP, and I was correct - lots and lots of gain, needs a lot of load to tone it down, THD relatively unimpressive. A simple cascoded common source amp has about the same THD and much better harmonic distribution, with fewer parts and headaches. If folks are interested, I'll post the sims for both. SRPPs appear to be a better match for the more humble jfets, something I've pretty much maintained all along. Any experiments I do in this vein with higher gm devices would be more in a spirit of exploration, than something I'd want to get behind in a big way.
Who said that Sunday was a day of rest? It was off to church this morning and then watching the Kings loose this afternoon/evening. Any NBA fans? My wife is at our house.
Hello Wrench,
What I likely build will start out in Beige Bag B2 SPICE then grow on a breadboard. At some point there will be iterations of RIAA preamplifiers and line level crossovers. I have done similar with Op-Amplifiers and tubes. I like the concept of discrete active components. The fets look doable because they sketch up in Spice like a triode. A SRPP looks like a SRPP. Fets look to offer quality performance, low noise at non lethal voltages that I can do with my grandson.
JFET’s in general is the object, not any one or two in particular. I bought the 2SK170’s because they are used in the B1 buffer and in Salas’ RIAA amplifier. They were affordable and were looking to be harder to find. I snatched them up.
The discussion of sorting was to consider if the workable parts could be put on the bench without parts selection being the most consuming part of the science project. I want to consider the big view then dig down on the details. My proposed sorting method was the most simple I came up with.
Did you say experiment? That is what this is.
OOPS If you would post your simulations that would be cool.
Thanks for the comments
DT
Hello Wrench,
What I likely build will start out in Beige Bag B2 SPICE then grow on a breadboard. At some point there will be iterations of RIAA preamplifiers and line level crossovers. I have done similar with Op-Amplifiers and tubes. I like the concept of discrete active components. The fets look doable because they sketch up in Spice like a triode. A SRPP looks like a SRPP. Fets look to offer quality performance, low noise at non lethal voltages that I can do with my grandson.
JFET’s in general is the object, not any one or two in particular. I bought the 2SK170’s because they are used in the B1 buffer and in Salas’ RIAA amplifier. They were affordable and were looking to be harder to find. I snatched them up.
The discussion of sorting was to consider if the workable parts could be put on the bench without parts selection being the most consuming part of the science project. I want to consider the big view then dig down on the details. My proposed sorting method was the most simple I came up with.
Did you say experiment? That is what this is.
OOPS If you would post your simulations that would be cool.
Thanks for the comments
DT
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