Patrick (EUVL) raised a valid point about the peculiar behaviour. It seems that despite the change in Idss, both Rs and Rd remain constant. I believe one might expect them to decrease for higher Idss, but the exact relationship between these values is not clear to me. Additionally, I suspect that the capacitances of the JFETs are not consistent either. Given these discrepancies, I've decided to remove the JFET model generator link. Despite my efforts it's clear that the model isn't perfect, and it's better to proceed without it rather than risk inaccurate results.
