Issues with simulation of Digital class D amplifier using Cadence AMS

[asenapati]

Hello!

I am simulating a closed loop digital class D amplifier system using ams.
The system consists of behavioural Verilog models for the digital portion (digital filters and pulse width modulator) of the system. The analog portion (the ADC and the antialias filter) is modelled using ideal components from analogLib.

I have the same system in Simulink which works as expected. However, the ams simulation doesn't seem to give the same result as Simulink. In fact, i know that the result is not what I expect.

I found out that if I make the first integrator of the delta sigma ADC using ideal VCVS with lower voltage limit, the system works. But that's not a practical case and my actual ADC (with transistor level modelling) has much higher output swing limits.

Any suggestions on how to debug would be really helpful.

Thanks & regards,
asenapati

 

[Mjjg]

Well this is very little information to go on. Simulink and AMS work very differently with regards to block triggering and such. Simulink calculates execution order and runs each block in the correct sequence. If you give veriloga(ms) blocks a sample period (using a @timer statement) the execution order is not guarantied and can in fact be quite random from run to run. This is one thing I saw way back when I transferred a design from simulink to cadence.

But since you talk about the ADC, I guess sample time might not be the issue here. In general, too ideal components tend to be a problem with spice solvers.

I think you will get way more help with this if you describe what behavior you where expecting, and what results you actually got. We need some more details to go on I'm afraid.

 

[asenapati]

Thanks for the quick reply, Mjjg

I don't know the execution order in cadence. What do you mean by @timer statement? Is it @posedge(clk) or something else? To confirm that the issue is not with the execution order of the spice solver, is there something that i can try?

To get rid of the issue with too many ideal components, I have tried replacing the amplifiers in the ADC with transistor level models. But it didn't help.

The ADC in the system is a third order continuous time delta sigma ADC. I noticed that if i replace the first (input side) opamp of the integrator of the ADC by a VCVS with voltage limit of 0.9+/-0.4V , the system is stable and transient waveforms at the output of the pulse width modulator and the antialias filter look correct. If the system works properly, the output of the antialias filter would look like a sinewave with some high frequency noise for a sine input. That's what i see when I do a transient simulation with the above.

On the otherhand, if i replace all the opamps in the ADC with transistor level models, i see some random signal at the output of the antialias filter. Replacing the first opamp with a VCVS with voltage limit of 0.9+/-0.7V doesn't help. Replacing the first opamp in the ADC by a VCCS with current limt and other opamps by transistor level models also give random output.

How should I go about it? Please let me know, if you need any more clarification.

Thanks & regards,
Ananya

 

[asenapati]

I am afraid.. the following statement that I made earlier isn't correct. With the following arrangement, it seems to work.

"Replacing the first opamp with a VCVS with voltage limit of 0.9+/-0.7V doesn't help. Replacing the first opamp in the ADC by a VCCS with current limt and other opamps by transistor level models also give random output."

 

[Mjjg]

@timer is an analog model way of performing some task periodically. If you have analog behavioral blocks that do something periodically but do not have a clock input, they probably use this statement. But I do not think this is the problem here. It is still very hard to give general advice when it seems to be a very specific problem, but what I can say is this.

0. Check your supply connections, silly mistake but I've made them plenty of times.
1. Check your connect module setup. Are you using the right connect modules for the supply you're using.
2. Replace you sine wave input with a constant, then a ramp. See if there is a difference.
3. Check signals through the chain, one block at a time. Do they look normal.
4. Cut feedback loops and see if blocks behave as expected under that condition.
5. Check your opamps in a testbench of their own. Can they drive the loads you have in your circuit.

Hope that helps.

 

[asenapati]

Thanks for the suggestions.

All analog blocks in my system are either modelled using ideal analogLib components or actual transistors. So there is no @timer statement used .

I have checked for suggestion 0,1,3. They seem to be correct.

I am checking the other points. I somehow feel that checking for point 5 might solve the issue as it is the first opamp in the ADC which is making a difference.

I will get back to you after following all your suggestions one by one.

 

[asenapati]

Hello!

I am able to simulate the digital class D loop using Cadence ams simulations and get the expected result. Following were the issues with my earlier attempts for which I was getting arbitrary outputs in ams simulations.

[1]. My ADC consisted of all ideal blocks. The amplifiers were made up of ideal vcvs with voltage limit or vccs with current limit and some bandwidth modelled. The quantizer was ideal too. The rest of the blocks in the system were modelled using behavioural verilog model. I noticed that, replacing atleast one amplifier in the ADC with a transistor level model helped in getting the expected result.

[2]. (Not sure about why this happens) I observed that enabling of skipdc in transient simulations is required to get the expected output.

[3]. At some point of time, I was messing up with the supply connections. I was connecting the bias current sources of the amplifiers in wrong polarity.

Correcting the above points helped.

Thanks & regards,
Ananya