I am simulating a closed loop digital class D amplifier system using ams.

The system consists of behavioural Verilog models for the digital portion (digital filters and pulse width modulator) of the system. The analog portion (the ADC and the antialias filter) is modelled using ideal components from analogLib.

I have the same system in Simulink which works as expected. However, the ams simulation doesn't seem to give the same result as Simulink. In fact, i know that the result is not what I expect.

I found out that if I make the first integrator of the delta sigma ADC using ideal VCVS with lower voltage limit, the system works. But that's not a practical case and my actual ADC (with transistor level modelling) has much higher output swing limits.

Any suggestions on how to debug would be really helpful.

Thanks & regards,

asenapati