Hi,
Anyone knows about a Bitstream design in the September and October 1990 issues of Hifi News? In this design the inverted L/R datastream is created by feeding the normal L/R datastream to both inputs of a two input nand gate, a 74HC132. The +L/-L and +R/-R datastreams are then created using a dual 64bit shift register (4517) and a dual 2 to 1 multiplexer (74HC157) and fed to a SAA7321 each. I will tray to build balance nonos TDA154x dac, so a copy of that article could help a lot, I guess. Thx all.
Anyone knows about a Bitstream design in the September and October 1990 issues of Hifi News? In this design the inverted L/R datastream is created by feeding the normal L/R datastream to both inputs of a two input nand gate, a 74HC132. The +L/-L and +R/-R datastreams are then created using a dual 64bit shift register (4517) and a dual 2 to 1 multiplexer (74HC157) and fed to a SAA7321 each. I will tray to build balance nonos TDA154x dac, so a copy of that article could help a lot, I guess. Thx all.
I've also made something like that. Took me a while to figure out what exactly. Long story 
Anyway, search in the digital section, schematics are there somewhere.
If you're target dac is 1541, there's even a pcb available.
It works, but there are improvements possible (reclock after dividing, 1541 PS arrangements and some more stuff). Going to do a version 2 someday...
edit: a HEF4517 can only be used for non-os: it's too slow otherwise.
Anyway, search in the digital section, schematics are there somewhere.If you're target dac is 1541, there's even a pcb available.
It works, but there are improvements possible (reclock after dividing, 1541 PS arrangements and some more stuff). Going to do a version 2 someday...
edit: a HEF4517 can only be used for non-os: it's too slow otherwise.
Yes I remember
It was before about a Year
the subject was the same...
Guido made some good version
but with the microcontroler if i
remember right
.
I think that we done some work on
decomposing the serial bus
without microcontroler supervising,
to parallel and after that again
merge to simultanious format
for TDA 1541A DAC...
.
the idea was to built the DAC not simetrical output...
.
that was based on one philips
document i think that You can find the topic...
.
anyway for that operation we need a 64 bit lenght
or 2x32 bit
because we have 2 words with 16 bit lenght...
.
16 bit L ... 16 bit R ... 16 bit L ... 16 bit R to
16 bit L ... 16 bit L ... 16 bit R ... 16 bit R
note TDA 7030 outputs to TDA 1540 dac
maybe the same format cn be used for
simultaneous data for TDA 1541A ?
It was before about a Year
the subject was the same...
Guido made some good version
but with the microcontroler if i
remember right
.
I think that we done some work on
decomposing the serial bus
without microcontroler supervising,
to parallel and after that again
merge to simultanious format
for TDA 1541A DAC...
.
the idea was to built the DAC not simetrical output...
.
that was based on one philips
document i think that You can find the topic...
.
anyway for that operation we need a 64 bit lenght
or 2x32 bit
because we have 2 words with 16 bit lenght...
.
16 bit L ... 16 bit R ... 16 bit L ... 16 bit R to
16 bit L ... 16 bit L ... 16 bit R ... 16 bit R
note TDA 7030 outputs to TDA 1540 dac
maybe the same format cn be used for
simultaneous data for TDA 1541A ?
Zoran said:
Hi,
Not a microcontroller, but prog logic. I used a gal but i had some 'extra' (some were useless
) features. Also the gal code was way too complex in the beginning.Was looking at a cpld for v2, to include DEM reclocking and some more stuff. But i got a pile of GAL's recently
But working on the preamp first and an output stage (prometheus D1). Someday...The schematic here is simpler, quite elegant. Dont go the parallel route anymore, the schematic here is i2s in to i2s out. Much easier. I certainly saved the picture.
Some thoughts
Mind you 32FS means that it wont work for 7210/7310/8412 output for building nos dacs (not shure what you're up to). That is 64FS (64 samples for one stereo 'sample', so 32 per left or right sample, so yes 16 bits used and 16 bits not used) format, so (as stated) 4562 required. I guess you can also use two 4517 daisy chained.
But keep an eye on the clockspeed! A HEF cmos chips is slow. I tried few HEF4517 and only one (philips) worked. At 64FS the clock is 'only' 2.8MHz. For higher clockspeeds (e.g. 8xOS at 32FS ~ 11MHz) you could daisychain some more (lots of...) 74 type shift registers or find a way to use the 4517 at 15V powersupply
Typical speeds: 5MHz at 5V, 15MHz at 15V.And the LSB is one bit o
Oops, sorry
this LSB thingie isn't an error, it's an offset. 43µV precisely (for a 2V rms output). It's no distortion!
43µV is such a small offset that any reasonable member of this forum wouldn't care about it.
-many of us have AC coupled amps
-some have discrete output stages, theyr intrinsec offset would be greater
-I even think opamps have higher offsets than this
43µV is such a small offset that any reasonable member of this forum wouldn't care about it.
-many of us have AC coupled amps
-some have discrete output stages, theyr intrinsec offset would be greater
-I even think opamps have higher offsets than this
Sorry about this, was only a joke. Please dont start the discussion again. Enough was said on this.
Just a remark to anyone looking at the schematic on the previous page: it is not fixed there. If you wanna know if that is bad or not, please search for the previous discussion on this.'
Back to i2s splitting (if needed)
Just a remark to anyone looking at the schematic on the previous page: it is not fixed there. If you wanna know if that is bad or not, please search for the previous discussion on this.'
Back to i2s splitting (if needed)
OK guys, lets move on a bit
Have you ever bild a I/V convector like this one based on current conveyor circuit alla Wadia swift current topology introdused in PA630/630A chip? This one is almost very good (sinusoid is not so good on bottom half (BTW, anyone knows how to deal with that?). I think that one of a goodies in this circuit is there is no global negativ feedback What do you think?
Have you ever bild a I/V convector like this one based on current conveyor circuit alla Wadia swift current topology introdused in PA630/630A chip? This one is almost very good
(sinusoid is not so good on bottom half (BTW, anyone knows how to deal with that?). I think that one of a goodies in this circuit is there is no global negativ feedback What do you think?
rfbrw said:
The problem is that you think about it the wrong way.
you think that the value is false because 2(10) gives -9 here, so you may think that the value is distorded, clipped, or whatever you want
but the reality is different
2(10) gives -9 : differential output is 19
2(9) -> -8 : differential is 17
2(8) -> -7 : differential is 15
2(7) -> -6 : differential is 13
the steps are equal, and of the correct value. it's no distortion at all, just a small offset fully negligible compared to the offset of your output stage.
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