Is very dificult compare mosfet specs from datasheets. This K factor is related to mosfet operating conditions (Tj, IF, dIF/dt)in order to estimate Qrr charge.
I would like to compare mosfet losses in my design, I can estimate using this:
http://www.diyaudio.com/forums/showthread.php?postid=1271703#post1271703
Calculating for minimum Trise Tfall for maximum dv/dt diode capability, I can calculate for crossover losses, but for diode recovery losses, is too much difficult to compare mosfet specs, because we need to obtain Qrr for every mosfet.
How can I obtain Qrr charge?
IF:10A
dIF/dt:? I suposse is related to complementary mosfet dv/dt voltage at TON ?(Is OK?)
Tj:50ºC aprox
Should I abandon this idea?
Thanks.
I would like to compare mosfet losses in my design, I can estimate using this:
http://www.diyaudio.com/forums/showthread.php?postid=1271703#post1271703
Calculating for minimum Trise Tfall for maximum dv/dt diode capability, I can calculate for crossover losses, but for diode recovery losses, is too much difficult to compare mosfet specs, because we need to obtain Qrr for every mosfet.
How can I obtain Qrr charge?
IF:10A
dIF/dt:? I suposse is related to complementary mosfet dv/dt voltage at TON ?(Is OK?)
Tj:50ºC aprox
Should I abandon this idea?
Thanks.
Hi! do you have heard about an avalanche effect in mosfets? 
This effect causes the mosfet to conduct (even with zero gate voltage) when dv/dt between source and drain is too small (ie voltage is changing too fast). 
This means, there is no way to avoid the crossconduction if switching time between two opposite mosfets is too small...
This effect causes the mosfet to conduct (even with zero gate voltage) when dv/dt between source and drain is too small (ie voltage is changing too fast). This means, there is no way to avoid the crossconduction if switching time between two opposite mosfets is too small... Are you sure about the details?
As far as I know, the avalanche effect take place if you run the MosFet at high voltages.
The effect is temperature depending and at lower temperatures it happens at lower voltages. During avalanche the device is clamping the voltage and dissipating the related power (heating like zener or TVS...). The allowed avalanche energies are usually specified in the data sheet for single pulse and repetitive pulses.
But if you are sure about something like a dv/dt-avalanche, I would be glad for a link to a related scientific paper, or application note, or own measurements/screen shots.
Usually dv/dt limitation is related to the short comings of the body diode during hard switching or related to triggering the parasitic BJT inside the MosFet...
CrossConduction is often happenning if the dead time is to short, means overlap times, during which Ugs of the upper and Ugs of the lower MosFet are above their threshold voltage.
But even if there is no overlap and perfect gate drive timing is in place, -even then you may get current peaks during switching.
a) Current peaks due to hard switching and the related reverse recovery peak of the diode. These peaks can be quite critical.
b) Current peaks related to the parasitic capacitances of the MosFet, of the layout and improper snubbers. These peaks are usually less critical than a).
As far as I know, the avalanche effect take place if you run the MosFet at high voltages.
The effect is temperature depending and at lower temperatures it happens at lower voltages. During avalanche the device is clamping the voltage and dissipating the related power (heating like zener or TVS...). The allowed avalanche energies are usually specified in the data sheet for single pulse and repetitive pulses.
But if you are sure about something like a dv/dt-avalanche, I would be glad for a link to a related scientific paper, or application note, or own measurements/screen shots.
Usually dv/dt limitation is related to the short comings of the body diode during hard switching or related to triggering the parasitic BJT inside the MosFet...
CrossConduction is often happenning if the dead time is to short, means overlap times, during which Ugs of the upper and Ugs of the lower MosFet are above their threshold voltage.
But even if there is no overlap and perfect gate drive timing is in place, -even then you may get current peaks during switching.
a) Current peaks due to hard switching and the related reverse recovery peak of the diode. These peaks can be quite critical.
b) Current peaks related to the parasitic capacitances of the MosFet, of the layout and improper snubbers. These peaks are usually less critical than a).
Hi Juanqui,
the K in your formula is in classD applications probably not as constant as people would appreciate...
If you run at low output currents (below the HF ripple of the filter), you will not have hard switching and K might go to zero.
At higher currents it may vary with the power level that you are targeting and hard switching will take place during a certain time of each period. Unfortunately Qrr is also not constant, but depending on temperature, current and di/dt.
But for comparison and MosFet selection, the Qrr value in the data sheet is helpful if you ensure that they are given at similar conditions.
Regarding simulation a reality:
Simulation is fine to get a better understanding. Amazinlgy many modern models show results that fit to reality even in the ns-range of fast switching. But reality catches you with all the undesired parasitics of your hidden schematic, means the layout.
You can expect several deviations between reality and simulation due to parasitic inductances and capacitances and the resulting resonances or peaks.
Regarding your topic IMHO now is a good time to play with a fast scope and real life measurements.
the K in your formula is in classD applications probably not as constant as people would appreciate...
If you run at low output currents (below the HF ripple of the filter), you will not have hard switching and K might go to zero.
At higher currents it may vary with the power level that you are targeting and hard switching will take place during a certain time of each period. Unfortunately Qrr is also not constant, but depending on temperature, current and di/dt.
But for comparison and MosFet selection, the Qrr value in the data sheet is helpful if you ensure that they are given at similar conditions.
Regarding simulation a reality:
Simulation is fine to get a better understanding. Amazinlgy many modern models show results that fit to reality even in the ns-range of fast switching. But reality catches you with all the undesired parasitics of your hidden schematic, means the layout.
You can expect several deviations between reality and simulation due to parasitic inductances and capacitances and the resulting resonances or peaks.
Regarding your topic IMHO now is a good time to play with a fast scope and real life measurements.
Hi ChocoHolic,
my thoughs are based on this doc http://www.irf.com/technical-info/appnotes/mosfet.pdf , but seems I have mixed the dv/dt capability and avalanche effect here Sorry for that 
Also, as I understand, the dv/dt capability has nothing with the body diode itself... The dv/dt capability depends only on the capacitance between drain/gate and on the gate plane resistance. So why this is called "Body diode dv/dt capability"?
Regards
my thoughs are based on this doc http://www.irf.com/technical-info/appnotes/mosfet.pdf , but seems I have mixed the dv/dt capability and avalanche effect here
Sorry for that Also, as I understand, the dv/dt capability has nothing with the body diode itself... The dv/dt capability depends only on the capacitance between drain/gate and on the gate plane resistance. So why this is called "Body diode dv/dt capability"?
Regards
Hm, on one hand this Application note is giving a overview, but for some reasons it is not telling anything about the reverse recovery of the body diode.
The body diodes usually are not really great diodes, - frankly speaking... except few exceptions they are poor diodes.
They have high Qrr values. If you look to the detail of the reverse recovery during hard switching - you will see a current peak towards the opposite direction. This current peak is removing the charge out of the junction. The diode remains conductive until this charge is removed. Typically the reverse recovery current peak is growing until the charge is removed. This means, the charge will be removed at a time with high reverse current. When this charge is removed, the diode becomes non conductive and the voltage across the diode can increase. The diode voltage is starting to increase, but the reverse recovery peak still has to decrease to zero. This decrease is taking place very fast , often called snap back, but still needs some ns. During these ns you have overlap of current and voltage and the allowed dv/dt during this time is also limited. Often this limitation is lower than the other discussed points in your AN.
STM is giving a brief info about what I described.
http://www.st.com/stonline/products/families/transistors/power_mosfets/related_info/fredmesh2.htm
At the end of the day we may wonder that MosFets survive so often
It is fact that the devices often survive unallowed situations.
But really reliable in the means of professional industry applications or automotive, you can only reach by considering all the limititations and in case of uncertainties - a detail discussion with the Device manufacturer can be a good idea.
The body diodes usually are not really great diodes, - frankly speaking... except few exceptions they are poor diodes.
They have high Qrr values. If you look to the detail of the reverse recovery during hard switching - you will see a current peak towards the opposite direction. This current peak is removing the charge out of the junction. The diode remains conductive until this charge is removed. Typically the reverse recovery current peak is growing until the charge is removed. This means, the charge will be removed at a time with high reverse current. When this charge is removed, the diode becomes non conductive and the voltage across the diode can increase. The diode voltage is starting to increase, but the reverse recovery peak still has to decrease to zero. This decrease is taking place very fast , often called snap back, but still needs some ns. During these ns you have overlap of current and voltage and the allowed dv/dt during this time is also limited. Often this limitation is lower than the other discussed points in your AN.
STM is giving a brief info about what I described.
http://www.st.com/stonline/products/families/transistors/power_mosfets/related_info/fredmesh2.htm
At the end of the day we may wonder that MosFets survive so often
It is fact that the devices often survive unallowed situations.
But really reliable in the means of professional industry applications or automotive, you can only reach by considering all the limititations and in case of uncertainties - a detail discussion with the Device manufacturer can be a good idea.
MOSFET-ANTIPARAELLEL DIODE
we found some mosfet modules have antiparallel diode function, it is high power and cheaper, you can develop smart circuit with it , maybe applied in QSC new multichannel pro products.
Microsemi have bigger modules same functions as this modules.expensive.
we have try some simliar circuit in our 2500w half bridge modules with IR2110 driver and run at 250KHz.
Better performance. recommand good current protection and multifeedback system, 0.5% THD+N at RMS power level delivery out.
we found some mosfet modules have antiparallel diode function, it is high power and cheaper, you can develop smart circuit with it , maybe applied in QSC new multichannel pro products.
Microsemi have bigger modules same functions as this modules.expensive.
we have try some simliar circuit in our 2500w half bridge modules with IR2110 driver and run at 250KHz.
Better performance. recommand good current protection and multifeedback system, 0.5% THD+N at RMS power level delivery out.
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