TIS is usually more correct 😊. Bruno Putseys takes DS to task over using that term.
In a current source (CCS) loaded VAS fed with a current mirror I guess you can get away without degeneration because the maximum TIS current is limited by the CCS under normal operation. In balanced or symmetrical TISs the degeneration acts to define the standing current. A good example would be a CFA using a TIS rather than the more normal TAS as used say in opamp versions. I’ve never had any issues with degeneration in this location other than pole-zero doublets on CFAs where I have tried MIC in a design that used a beta helper. In that specific case, I just ditched the MIC comp and went for TMC.
In a blameless type amp you can use degeneration in the TIS amp to balance the LTP collector currents which may get you a few ppm lower distortion.
In a current source (CCS) loaded VAS fed with a current mirror I guess you can get away without degeneration because the maximum TIS current is limited by the CCS under normal operation. In balanced or symmetrical TISs the degeneration acts to define the standing current. A good example would be a CFA using a TIS rather than the more normal TAS as used say in opamp versions. I’ve never had any issues with degeneration in this location other than pole-zero doublets on CFAs where I have tried MIC in a design that used a beta helper. In that specific case, I just ditched the MIC comp and went for TMC.
In a blameless type amp you can use degeneration in the TIS amp to balance the LTP collector currents which may get you a few ppm lower distortion.
I wonder if you can't use a common-mode loop instead of throwing away loop gain with shunt resistors and local feedback.
Edmond Stuart (RIP) used that in his balanced VFAs that used current mirror loads for the LTPs but it does add extra complexity. I am a reductionist at heart so I tend to trade a few ppm higher distortion for more simplicity (up to a point).
YMMV.
YMMV.
I've been taught to design orthogonally, which means I usually end up with very simple signal schematics and huge amounts of supporting circuitry around them. For example, in my previous job, I once had to present a crystal oscillator design of mine to a customer. I showed them a schematic with dozens of transistors and said: 'This is a single-transistor crystal oscillator. The single transistor is there.' Everything else was supporting circuitry, such as biasing and amplitude control circuitry. It was to be integrated on a chip, so transistors were cheap, capacitors were expensive.
If the same side driver draws a lot of current through it's base, the VAS can supply an indefinite amount of current. This is where it's useful to have current limiting. However you can also consider what has to happen in the EF before it draws that much current. Often by that time you would expect something else to be broken. If you have overcurrent protection that shunts the drivers, then you will probably want current limiting of some sort on the VAS. If the drivers clip before the VAS, it can also dump indefinite currents into the drivers and out their collectors.
One problem with a degenerated VAS is that during overload or clipping, excess input current will flow out the collector rather than the emitter, causing more phase inversion which can lead to clip latching and sticking behavior. We dealt with this on the Wolverine.
I use VAS purely because everyone is already familiar with the term, it's hard enough to describe the fine points of operation without heaping confusion on top of confusion. If someone takes issue with the word I use even though it doesn't confuse them or anyone else, then they probably weren't interested in what I was saying to begin with. I save my energy for those who can actually benefit.
Besides, A VAS has a voltage gain limit which can overtake transimpedance at low frequencies, and a current gain limit that overtakes transimpedance at low load impedances. And the distortion mechanism that dominates may be rooted in the voltage gain or current gain rather than the transimpedance. None of these subtleties are dealt with by using a different acronym. When I go into details like this, I explain it longform, I don't use acronyms and expect everyone to understand.
One problem with a degenerated VAS is that during overload or clipping, excess input current will flow out the collector rather than the emitter, causing more phase inversion which can lead to clip latching and sticking behavior. We dealt with this on the Wolverine.
I use VAS purely because everyone is already familiar with the term, it's hard enough to describe the fine points of operation without heaping confusion on top of confusion. If someone takes issue with the word I use even though it doesn't confuse them or anyone else, then they probably weren't interested in what I was saying to begin with. I save my energy for those who can actually benefit.
Besides, A VAS has a voltage gain limit which can overtake transimpedance at low frequencies, and a current gain limit that overtakes transimpedance at low load impedances. And the distortion mechanism that dominates may be rooted in the voltage gain or current gain rather than the transimpedance. None of these subtleties are dealt with by using a different acronym. When I go into details like this, I explain it longform, I don't use acronyms and expect everyone to understand.
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For an amp with complementary LTPs, you can have 2 DC NFB from 2 different places to define the bias. I had a design like this.
Thread 'Symmetrical Blameless, TMC'
https://www.diyaudio.com/community/threads/symmetrical-blameless-tmc.419716/
First of all .5uH or 500nH of wiring inductance??? This is absurd, you would intentionally need to be coiling wire in the chassis to get it that high. A better estimate is roughly 25nH/inch for chassis wiring. If this was routed out properly on a PCB the track length would be kept reasonably short.
Second I would avoid putting any significant shunt stabilization network on the predriver base as this will load down the VAS/TIS at 20kHz and degrade the distortion.
Third, I would focus the EF3 stabilization network on the driver base while trying to keep the series resistor as low as possible without compromising stability to minimize losses. Also using 30MHz transistors typically requires a 1-10ohm base resistor on the all the outputs and of course use a zobel on the output of the EF3 with each stage is properly bypassed.
Here are some configurations for the driver base stability networks
1) series R and shunt C
2) series R and shunt RC zobel (what you have shown)
3) series parallel RC
1) and 2) typically requires a speed up cap in parallel with the predriver bias resistor to be able to discharge the shunt C effectively.
Fourth, I would analyze the loop gain where the phase goes to 180°. I would shoot for a minimum of 10dB of gain margin and look in this region for any peaking, adjust the stability network until the peaking is appropriately squashed. Add additional capacitance on the output of the EF3 before the output inductor to see how sensitive it is to peaking/oscillation (this capacitance is not actually installed on the design). Stable designs can handle a fair amount of capacitance before breaking into oscillation.
Bypassing the VAS/TIS emitter resistors as Keantoken suggests with a cap can push any peaking associated with the VAS/TIS out much higher in frequency. This is more effective with higher values of emitter resistors, low emitter resistor values may not need any bypassing.
I'm not discounting transient/time domain simulations. I use both AC and transient/time domain simulations to determine stability.
Lastly be wary of the manufacturers spice models. Bob Cordell and Keantoken have greatly improved the accuracy of these models. Using accurate models will allow you to create a better stability network which will get you closer to the final result.
Jeremy
Second I would avoid putting any significant shunt stabilization network on the predriver base as this will load down the VAS/TIS at 20kHz and degrade the distortion.
Third, I would focus the EF3 stabilization network on the driver base while trying to keep the series resistor as low as possible without compromising stability to minimize losses. Also using 30MHz transistors typically requires a 1-10ohm base resistor on the all the outputs and of course use a zobel on the output of the EF3 with each stage is properly bypassed.
Here are some configurations for the driver base stability networks
1) series R and shunt C
2) series R and shunt RC zobel (what you have shown)
3) series parallel RC
1) and 2) typically requires a speed up cap in parallel with the predriver bias resistor to be able to discharge the shunt C effectively.
Fourth, I would analyze the loop gain where the phase goes to 180°. I would shoot for a minimum of 10dB of gain margin and look in this region for any peaking, adjust the stability network until the peaking is appropriately squashed. Add additional capacitance on the output of the EF3 before the output inductor to see how sensitive it is to peaking/oscillation (this capacitance is not actually installed on the design). Stable designs can handle a fair amount of capacitance before breaking into oscillation.
Bypassing the VAS/TIS emitter resistors as Keantoken suggests with a cap can push any peaking associated with the VAS/TIS out much higher in frequency. This is more effective with higher values of emitter resistors, low emitter resistor values may not need any bypassing.
I'm not discounting transient/time domain simulations. I use both AC and transient/time domain simulations to determine stability.
Lastly be wary of the manufacturers spice models. Bob Cordell and Keantoken have greatly improved the accuracy of these models. Using accurate models will allow you to create a better stability network which will get you closer to the final result.
Jeremy
0.5uH might be the worst case allowed here if the VAS is on a separated board. The signal always need a return current. The return current would go through ground lead and power rail. Thus it is a loop. If you are not careful, 0.5uH is possible.
I figured that 220pf would be the max cap is allowed at this position. Thus I use 0.5uH for demonstration.
My formula is use 47 Ohm value for both the base and shunt resistor. For the cap in shunt position, use 47p per 0.1uH inductance ahead. As said in post #48, you get output inductance from the prior EF stage even the wire inductance is ignored.
You have two feedback networks setting the voltage gain from input to output. What happens when, due to resistance tolerances, they disagree and one wants a gain 2 % above and the other 2 % below nominal?
Some techniques to limit TIS current
https://hifisonix.com/wp-content/uploads/2024/06/Fast-TIS-Stages-for-Audio-Amplifiers.pdf
https://hifisonix.com/wp-content/uploads/2024/06/Fast-TIS-Stages-for-Audio-Amplifiers.pdf
Good question.
In that original post, I have a bypass cap at the traditional VBE multiplier position to absorb the fluctuations.
In the case of 2 opamps (
Post in thread 'Symmetrical Blameless, TMC'
https://www.diyaudio.com/community/threads/symmetrical-blameless-tmc.419716/post-7844946
), it is dealt with through 2 extra resistors that highlighted in that post.
Hi @MarcelvdG, merry Christmas.
You are right. I might have overlooked this. It needs to be revisited at some point. 2 miller caps alone would cause competition on the current at dynamic conditions even the idle current is well defined.
Finally, CFP or Sziklai pair.
You can see even a small inductor can cause instability with CFP. In the simulation above, there is no load attached to the output yet!
Just as predicted in the post #10. The negative impedance at the input is proportional to the gm. As the CFP has very large gm, this thing is unstable.
Here are the fixes.
Below C3 47pf is good enough to counteract anything below 0.1uH from the input.
Option 1.
Option 2.
PS: Using CFP as the output stage, adding an output inductor is highly recommended. You want to avoid any possible capacitive load attached to the output directly.
You can see even a small inductor can cause instability with CFP. In the simulation above, there is no load attached to the output yet!
Just as predicted in the post #10. The negative impedance at the input is proportional to the gm. As the CFP has very large gm, this thing is unstable.
Here are the fixes.
Below C3 47pf is good enough to counteract anything below 0.1uH from the input.
Option 1.
Option 2.
PS: Using CFP as the output stage, adding an output inductor is highly recommended. You want to avoid any possible capacitive load attached to the output directly.
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