So I want to use an op amp for voltage gain and IPS. This is what I have come up with. Just on 20V rails for now, the op amp will remain on low voltage rails and the rest on 40V. The common base stage for a little extra voltage gain then an output stage. This amplifier shows promise with 0% distortion in the first 0.3s of simulation then it oscillates. What ways could I use to stabilize it? I tried the cap over the feedback resistor shown but it didn't do anything at any value. I have also tried a cap going from the output of the opamp to the - input and this keeps it from total oscillation but I can see high frequencies on top of the waveform with it with more distortion.
Can anyone help to stabilize this amp?
Thanks.
Can anyone help to stabilize this amp?
Thanks.
Firstly ( without a current booster ) the opamp looped at the desired gain should be stable with enough phase margin.
Seconly, adding the current booster in the loop will decrease this phase margin.
Slower BJTs, more stages mean more phase lag, hence less stablility if any.
The opamp should be slower than the current booster. A crude way to stabilize is to add a cap at the output of the opamp to ground.
Seconly, adding the current booster in the loop will decrease this phase margin.
Slower BJTs, more stages mean more phase lag, hence less stablility if any.
The opamp should be slower than the current booster. A crude way to stabilize is to add a cap at the output of the opamp to ground.
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Your VAS transistors (Q7, Q8) need a cap from collector to base, in the neighborhood of 47 to 68 pF. ANY amplifier needs this. Increase R9 - your closed loop gain will need to be 30 or more with this circuit, even if the opamp is unity gain stable. Reduce C4 to the 6 to 20 pF range, and connect it to the VAS output (not the speaker out). The high frequency feedback needs to NOT include the phase shift in the output transistors - it's alomst always too much and will push it past 180 degrees. This is very critical with any of these op amp input high feedback factor designs. You will need to experiment with C4 both in the simulator and in the actual circuit layout. Loop gain analysis will tell you the range for stability, but it is so layout parasitic dependent that it's faster to just build and experiment.
I've also played around with a very similar topology, and agree it is sort of interesting and has some potential, although many here will not agree.
Try a small cap (5 pf or so) from either VAS collector back to the positive input of the op amp. Play around with that, possibly in conjunction with the aforementioned miller cap from collector to base of the VAS transistors. You may also have to go back to the cap across the feedback resistor as well. This topology probably has about 120 dB or so of open loop gain, so it's not the easiest to stabilize, but it can be done. Post the .asc file for LTSpice if you have one.
Try a small cap (5 pf or so) from either VAS collector back to the positive input of the op amp. Play around with that, possibly in conjunction with the aforementioned miller cap from collector to base of the VAS transistors. You may also have to go back to the cap across the feedback resistor as well. This topology probably has about 120 dB or so of open loop gain, so it's not the easiest to stabilize, but it can be done. Post the .asc file for LTSpice if you have one.
Sure, no prob. Couple of other thoughts - I think you should try grounding the point where the cathode of D2 and the anode of D1 are connected. I think that will help contain the overall DC offset in a real world implementation. Also in a real world implementation, the pot on the Vbe multiplier is very risky the way you have it drawn. If the wiper goes open circuit for just a few microseconds, as in a noisy pot, the Vce of that transistor goes up far enough to destroy some downstream silicon.
This circuit can't work.
1. Current through R4 and R11= (10-0.6)/330=28mA. Voltage drop on R3 (R6) is 28mA*1K=28V . It is not possible because supply voltage is 20V. Even it would be possible (supply voltage 40...50V) BC8... transistors will burn in this case. And Q7 (Q8) collector current will be (28-0,6)/470=58mA. Q7 (Q8) will burn too. And max output voltage will be less than (40..50)-28...
2. Current through zeners =(20-10)/47=212mA. WHY?
Replace each zeners with LED or two diodes (1n4148) and R14, R15 ~4.7k. And now You will can try to stabilize with methods posted by others guys above.
Good luck!
p.s. and sorry, my english is ...
1. Current through R4 and R11= (10-0.6)/330=28mA. Voltage drop on R3 (R6) is 28mA*1K=28V . It is not possible because supply voltage is 20V. Even it would be possible (supply voltage 40...50V) BC8... transistors will burn in this case. And Q7 (Q8) collector current will be (28-0,6)/470=58mA. Q7 (Q8) will burn too. And max output voltage will be less than (40..50)-28...
2. Current through zeners =(20-10)/47=212mA. WHY?
Replace each zeners with LED or two diodes (1n4148) and R14, R15 ~4.7k. And now You will can try to stabilize with methods posted by others guys above.
Good luck!
p.s. and sorry, my english is ...
I have been ill with flu for the past week so haven't been able to do anything. I have now though and everything I try, capacitors everywhere in all combinations of all values will not stabilize this amplifier. Interestingly it oscillates if the bias is sent too high even if there is no signal present, it also takes longer to oscillate driving 8ohm than 4 so could be a current thing.
Any ideas?
Any ideas?
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