Help please with my poorly Stasis 2

[gary s]

Yeh, I am aware of that product and have used them with no problems. Whether the member wants to do all the build, with chassis metalwork etc is the issue.

 

[amplidude]

Yes, that's his discission alone.. I'm unsure what happens if failure occures, the leach outputs nothing if one of the rails fail.

 

[TheFinisher]

Building a chassis and casework wouldn’t be a problem, do these solutions have a detrimental effect on the sound at all ?

 

[amplidude]

Close to unmeasurable, there's a thread here on diyaudio on ssr protection

 

[amplidude]

If you want to learn more about this check rod elliots site, there is great info on this subject to

 

[gary s]

Heh Zen Mod, can we enlist your help again please. The member has both OS biased up at around 50 deg C on the heatsink with each OS loose on the bench. However even after a few hours the bias still moves and has to be tweaked on the P2 pot. Also the DC mV offset volts can only be adjusted down to a minimum of around 110mV - I would like too get it below 50 mV if possible.

The member has messaged another member who has built one from scratch (not cascode output like the Stasis 2 but conventional) he has said the temp is not stable while on the bench separately but had to be bolted all back in the chassis with the lid on to get to a stable point and then bias and offset was adjusted again. - any comments on this.

Also to get the DC mV offset lower, what resistor would we need to change the value of ( I think Mr Pass has mentioned R8, but not a value) or would it be better to adjust R5. At the moment the pot P1 is at max resistance to get the lowest mV DC offset at around 110mVDC at the speaker terminals. What value resistor would you suggest to be appropriate? Also another point - in your marked up schematic below you show the JFet currents at 2.16mA, I sent over to the member matched pairs (better than 1%) with an Idss of around 8mA - do we need to increase the input stage currents - or is this all OK, many thanks for your advice. Please let us know if you need any further info on measurements from Andy there in the UK.

 

[Zen Mod]

The member has both OS biased up at around 50 deg C on the heatsink with each OS loose on the bench

it must be done finally with everything assembled , approach "let it cook with lid on, open the lid- re-set, close the lid, let it cook with lid on, open the lid- re-set, close the lid, let it cook with lid on, open the lid- re-set, close the lid, enjoy

attached what need to be attached, look down

any comments on this.

practically same as I was saying

At the moment the pot P1 is at max resistance to get the lowest mV DC offset at around 110mVDC

as Dr. Haus use to say, Everybody lies

Someone here is lying - pot going to max direction is ending in output DC Offset rising; accordingly - if one wants to minimize positive offset, pot needs to go to minimal value position

So, I need firm confirmation that DC Offset is positive (so, yes, literally confirmed that red probe is on output positive terminal, and black probe is on negative output terminal, so GND), and then I need confirmation what's actual resistance of P1 - is it maxed or minimized

What I will do - assemble everything in case, conduct proper setting procedure and them - actually knowing amp behavior in Temp, equilibrium, decide what to do if DC Offset is still a problem

swapping places of LTP Jfets will be first thing to do, and see what's outcome

 

[gary s]

Thanks for the reply Zen Mod, as always greatly appreciated.

Andy, the member will need to confirm, if the output DC mV offset is indeed pos or neg and at the minimum value and then he can actually measure the P1 offset pot resistance - it will be either zero ohms or 500 ohms. As I mentioned the jfets are matched to 1% that I sent him.

He is asleep now so is going to try again Sat morning his time.

Until tomorrow, we will get some more updates, I am sure Andy will post here with updates as he goes.

 

[TheFinisher]

Ok here goes .

P1 pot minimum resistance is 000.2ohms
P1 pot maximum resistance is 0.479 k ohms

P2 pot has the same resistance values
I believe these identical pots are 25 turn .

This measurement was taken 1 hour after powering off the amp …

P1 R5 & Q7 right channel = 340.3ohms
P1 R5 & Q7 left channel = 394.6 ohms

Offset ( I don’t understand why they’re different)
Measurements taken whilst heatsinks are at around 50c
Minimum and maximum offset when turning P2 pot

Left channel
-105.6mv
-069.8v

Right channel
033.1mv
-071.8v

Q1 and Q2 Jfets swapped around on both boards before these measurements were taken, please help me understand why I was asked to do this when they’re a matched pair and both are identical 😁

Photo to show that dmm probes are on the speaker terminal ( RED ) for the positive and ( BLACK ) for the negative ( yellow and brown) when measuring the offset .

I’ve no doubt that I’ve done something wrong 😑

 

[william2001]

I'm a little confused. Gary's post at #426 says "P1 is at max resistance". But finisher says:

P1 R5 & Q7 right channel = 340.3ohms
P1 R5 & Q7 left channel = 394.6 ohms

???

 

[Zen Mod]

just set it to minimum possible offset and be done with

105mV is absolutely fine, if it stays as that in all temperatures

 

[TheFinisher]

That’s what I’ve been doing Zen.
Now to strip down each channel and remove each transistor ( for critical matching) 😩

 

[gary s]

Andy, just to confirm, you have shown P1 resistance values which I assume are at the offset voltages you show with P2 bias adjusted for min bias and max bias.

This is not clear to me as the P1 value is not showing at zero or max to get minimum DC offset.

Also what happened to the offset reading after swapping Q1 and Q2? Did it make any difference?

But as ZM has said we can live with a max offset of 105mV, provided it stays like that, bolt it all together with the lid on and monitor over a few hours. Jon Soderberg does this over a 6 hour period with minor tweaks to bias and offset till the amp stabilizes - he uses a slightly more conservative heatsink max temp of 46 deg C - which was the Threshold factory spec back in those days. Nelson Pass has a rule of thumb figure of 50 deg C at max bias level.

 

[TheFinisher]

after Jfets swapped
Left channel
-105.6mv
-069.8v

Right channel
033.1mv
-071.8v

Before swap out
Left
-072.2mv
-112.3mv

Right
-017.9mv
-105.9mv

 

[gary s]

Thanks Andy, to be clear about this - you show two mV values for each channel - what do these correspond to?

 

[TheFinisher]

I don’t know myself now Gary , like I said I’ve got so many measurements written down now that I’m confused 🫤.

 

[gary s]

This is confusing as I assume all readings were done at your heat sink temp of approx 50 deg C?

Should only have 1 offset reading per channel with P1 adjusted to give the lowest possible value of Dc offset - and that should be with the offset pot P1 at the end of its multiturn travel.

 

[Zen Mod]

for ooompteenth time, time for me to switch brain off and grab a big cup of popcorns

 

[TheFinisher]

The strip down has begun…..

 

[gary s]

Yes the current sharing in the OS was way off, so we are going to measure the Hfe of each transistor and see how many matched sets we can get with the current number. Jon Soderberg has advised matching should be better than 20% difference and 10% is great. Any transistor that is more than 20% out should not be used, so we might have to buy some more - but we will see what we can achieve. That is matching N to N and P to P types, it is not necessary or possible to match N to P as the P types always have a higher gain than the N types for the complementary pair.

For the MJ15022/23 types, Jon uses 35-70 Hfe for NPN and 50-90 Hfe for PNP - within 10 to 20% of each other in the set is fine.