Please see attached for more info.
EDIT: Maybe not the whole story though. Ferrite beads that saturate at some undefined current and therefore cause problems have be reported. Also, hysteresis distortion/noise as a possible issue hasn't been ruled out yet.
In addition, some of the issues discussed in the attached article may be becoming more relevant for lower frequency circuits as semiconductor manufacturers continue to shrink dies and transfer old parts over to newer manufacturing processes. The part number may stay the same, but risetime might get significantly faster as a result.
EDIT: Maybe not the whole story though. Ferrite beads that saturate at some undefined current and therefore cause problems have be reported. Also, hysteresis distortion/noise as a possible issue hasn't been ruled out yet.
In addition, some of the issues discussed in the attached article may be becoming more relevant for lower frequency circuits as semiconductor manufacturers continue to shrink dies and transfer old parts over to newer manufacturing processes. The part number may stay the same, but risetime might get significantly faster as a result.
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As reading:
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Instead, I have determined what the “ripple” requirements of a circuit are and designed the power delivery system to meet this requirement.
What should the vendor have done to ensure that its application note correctly advised its customers?
The first thing an IC vendor needs to do is understand the power delivery needs of each IC. This includes maximum delta I that the circuit may demand of the power delivery system as well as at what frequencies and the maximum allowable delta V (ripple). Without this, it is not possible to design a power delivery system.
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Just ask AKM / ESS about this regarding ripple (voltage and current) on power pin's, analog output and VRef 😱 as radio silence.
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Instead, I have determined what the “ripple” requirements of a circuit are and designed the power delivery system to meet this requirement.
What should the vendor have done to ensure that its application note correctly advised its customers?
The first thing an IC vendor needs to do is understand the power delivery needs of each IC. This includes maximum delta I that the circuit may demand of the power delivery system as well as at what frequencies and the maximum allowable delta V (ripple). Without this, it is not possible to design a power delivery system.
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Just ask AKM / ESS about this regarding ripple (voltage and current) on power pin's, analog output and VRef 😱 as radio silence.
Some info on operating with bypass caps above resonance:
https://www.sigcon.com/Pubs/straight/resonance.htm
https://www.sigcon.com/Pubs/straight/resonance.htm
Hey Markw,
I watch this thread with great interest, especially at your reclocker board and I deeply thank you for your effort, even more because it is an "open source" project, but I have some questions regarding the reclocker board and the components used:
1) why did you chose LP5907 instead of TPS7A20? Even the LP5907 datasheets recommends using TPS7A20, it has better PSRR and also they are pin compatible
2) when using the reclocker for synchronous recloking, wouldn't make sense to also include an insolated output on the board for the MCLK? so that the MCLK ground plane will be shared only with the reclocker board and what follows after (the DAC) and not with the I2S source as well
3) I suppose you put the option to invert the MCLK because the rest of the signals will also be inverted due to the TLP2767. What is the porpoise for the second inverted U2, as it will only achieve the same state as the original MCLK ?
4) aren't you concern that you "alter" the nice MCLK signal with a inverter IC?
5) why not use non inverting octocouplers so that the MCLK wouldn't need to be inverted and/or further confuse users of the inverted isolated signals?
Thank you !
I watch this thread with great interest, especially at your reclocker board and I deeply thank you for your effort, even more because it is an "open source" project, but I have some questions regarding the reclocker board and the components used:
1) why did you chose LP5907 instead of TPS7A20? Even the LP5907 datasheets recommends using TPS7A20, it has better PSRR and also they are pin compatible
2) when using the reclocker for synchronous recloking, wouldn't make sense to also include an insolated output on the board for the MCLK? so that the MCLK ground plane will be shared only with the reclocker board and what follows after (the DAC) and not with the I2S source as well
3) I suppose you put the option to invert the MCLK because the rest of the signals will also be inverted due to the TLP2767. What is the porpoise for the second inverted U2, as it will only achieve the same state as the original MCLK ?
4) aren't you concern that you "alter" the nice MCLK signal with a inverter IC?
5) why not use non inverting octocouplers so that the MCLK wouldn't need to be inverted and/or further confuse users of the inverted isolated signals?
Thank you !
@stefan646
Thank you for the questions. I will try to respond:
1. I could have used a different voltage regulator; no study was done to find the lowest cost regulator that would be good enough. Regarding PSRR, I use external pre-regulators before the local regulators on the boards shared in the thread. Thus the input voltage to the local regulators has already been regulated once, which means PSRR is not so important in this case. Also, I had LP5907 in stock and used it for another board already. So far, looks like it works quite well if loaded with a suitable output resistor to ground to optimize its regulation performance. Might also mention that I tend to pre-regulate the input voltage to the boards a little on the low-ish side, maybe around 4.7v. That way the voltage drop across the local regulators is low, so their power dissipation can be low even though I may be running a lot of current through them if needed to optimize regulation performance.
2. Isolators add jitter. MCLK needs to be as low jitter as possible at the reclocker, and also if needed inside the dac. So we have to find a way so that MCLK can be on the same ground plane as the dac.
3&4. The option to invert MCLK is to to add a time delay, if needed. Inverters have the lowest jitter of any logic device, so if well designed then passing MCLK through one or two inverters can be used to make selectable a time delay while still keeping jitter pretty low. The reason a time delay might be needed is so that the setup and hold requirements of the D Flip Flops can be met. Ideally its probably better to adjust a time delay somewhere else, but for convenience and or testing purposes two inverters are available on the reclocker board.
5. Its possible to use a different optocoupler, or else an inverter could be put after the existing optocouplers. However, the D filp flops have inverting and non-inverting outputs which can be used if an inversion is needed.
Beyond the above, there are various ways to design a reclocker. The essence of it is that D Flip Flops are used to sample the state of an input signal at a time determined by MCLK. Each input signal must be sampled when it is high and again when it is low, thus MCLK must be at least at twice the frequency of the input signals to be sampled and reclocked.
Thank you for the questions. I will try to respond:
1. I could have used a different voltage regulator; no study was done to find the lowest cost regulator that would be good enough. Regarding PSRR, I use external pre-regulators before the local regulators on the boards shared in the thread. Thus the input voltage to the local regulators has already been regulated once, which means PSRR is not so important in this case. Also, I had LP5907 in stock and used it for another board already. So far, looks like it works quite well if loaded with a suitable output resistor to ground to optimize its regulation performance. Might also mention that I tend to pre-regulate the input voltage to the boards a little on the low-ish side, maybe around 4.7v. That way the voltage drop across the local regulators is low, so their power dissipation can be low even though I may be running a lot of current through them if needed to optimize regulation performance.
2. Isolators add jitter. MCLK needs to be as low jitter as possible at the reclocker, and also if needed inside the dac. So we have to find a way so that MCLK can be on the same ground plane as the dac.
3&4. The option to invert MCLK is to to add a time delay, if needed. Inverters have the lowest jitter of any logic device, so if well designed then passing MCLK through one or two inverters can be used to make selectable a time delay while still keeping jitter pretty low. The reason a time delay might be needed is so that the setup and hold requirements of the D Flip Flops can be met. Ideally its probably better to adjust a time delay somewhere else, but for convenience and or testing purposes two inverters are available on the reclocker board.
5. Its possible to use a different optocoupler, or else an inverter could be put after the existing optocouplers. However, the D filp flops have inverting and non-inverting outputs which can be used if an inversion is needed.
Beyond the above, there are various ways to design a reclocker. The essence of it is that D Flip Flops are used to sample the state of an input signal at a time determined by MCLK. Each input signal must be sampled when it is high and again when it is low, thus MCLK must be at least at twice the frequency of the input signals to be sampled and reclocked.
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Regarding this one point, I2SoverUSB isolates the dac reclocker and I2S ground plane from USB ground (which is important). Eventually, the dac ground plane will be shared with the dac load device anyway, be it an external preamp or whatever. What one needs to look out for most in this regard are ground loop problems. I do go to a lot of effort to avoid those. All the external pre-regulators are isolated from each other. Grounds are only connected at the load boards. There is one dedicated transformer winding for each pre-regulator circuit. There is also a Hum Breaker circuit to help keep AC line noise out of the dac ground plane.
That said, and to your point, I could go a bit farther with caution by isolating the 45/49MHz PLL output that feeds the I2SoverUSB external clock input. Its also possible to isolate the frequency select output on I2Sover USB so it would be more isolated from the dac ground plane. However, not doing those things doesn't seem to be a problem. What does need to be looked out for is radiated EMI/RFI coming out of USB board, and or the PCM2DSD board. That's why they are located some distance from the dac board. Also I have a steel box I can put over the USB board and PCM2DSD for a bit more shielding.
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One more thing I would like to remind folks about is that its important to keep clocks running 24-hours/day. We had a power failure here yesterday for 7 hours. When I was able to bring the system back up, it didn't sound its best. After running overnight its now back to its best sound and imaging. I'm pretty sure a lot of the recovery time had to do with clock oscillators restabilizing. Also regarding the clocks, Iancanada also makes the same point about leaving the power on for his clocks. Moreover, my understanding from Andrea Mori is that phase noise of SOA oscillators may keep measurably improving over a period of weeks if they are kept running all the time. Even Topping D90 keeps the dac running all the time unless its turned off from the switch on the back. Turning it off from the front or using remote appears to mainly just turn off the display and mute the outputs.
Reason I'm bringing this up now is because there a forum member thinking about using batteries to power his MarcelvdG RTZ dac, along with my boards. Not sure if he will find a way to keep clocks running while batteries are charging. All I can do is share what information and or experience I have and hope that folks will take it under consideration.
Reason I'm bringing this up now is because there a forum member thinking about using batteries to power his MarcelvdG RTZ dac, along with my boards. Not sure if he will find a way to keep clocks running while batteries are charging. All I can do is share what information and or experience I have and hope that folks will take it under consideration.
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I was referring to connecting the MCLK to the I2SoverUSB so that the reclocking will be synchronously by adding another isolator( in reverse so in total 4 inputs and 1 output). In know that isolators add jitter, but then a compromise should be done : clean and nice MCLK for I2SoverUSB with shared grounds vs isolated grounds but a MCLK with some jitter for the I2SoverUSB
Sure. It would be fine to isolate the MCLK sent to I2SoverUSB. I just didn't find it necessary in this case, since no ground loop is produced with only one ground connection. What does matter though is to run I2SoverUSB from two mutually isolated linear power supplies. IOW, don't run the dirty side of I2SoverUSB from USB power. That does make a difference.
One of the problems I sometimes see is that people focus a lot of attention on things that are possible problems, but maybe not actual problems in reality. The same people sometimes miss other things which are real problems. It just seems to be part of human nature. For example, there was a whole lot of discussion in the RTZ dac thread about running signals on the PCB surface layer under the shift registers (instead of routing bypass currents on that layer). Turns out testing shows its a very minor matter in this case. Its possible to get fabulous sound out of the RTZ dac by not doing some of the things multiple people thought should be better.
For myself, I do a lot of testing to try to find out what is a problem and what is not. Then I share many of my observations here in the forum. People can choose to believe me or not. Doesn't matter. At least I tried.
One of the problems I sometimes see is that people focus a lot of attention on things that are possible problems, but maybe not actual problems in reality. The same people sometimes miss other things which are real problems. It just seems to be part of human nature. For example, there was a whole lot of discussion in the RTZ dac thread about running signals on the PCB surface layer under the shift registers (instead of routing bypass currents on that layer). Turns out testing shows its a very minor matter in this case. Its possible to get fabulous sound out of the RTZ dac by not doing some of the things multiple people thought should be better.
For myself, I do a lot of testing to try to find out what is a problem and what is not. Then I share many of my observations here in the forum. People can choose to believe me or not. Doesn't matter. At least I tried.
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Continuous power supply to clocks is a good way to achieve better performance, you know.
But in this design, if two clocks are installed, crosstalk effects occur.
This is due to the fact that two signals enter to the Clock Buffer (LMK1C1104PWR).
The first one is the active clock and the second one is the inactive clock
reduced by about 70dB (by relay G6K-2F-RF-DC5 - this is what the documentation says).
See isolation for 25MHz is about 70dB:
The same can be seen in the signal spectrum:
But when we take out the inactive clock from PCB we have:
As you can see, 70dB isolation is not enough...
We can improve this by using one relay per clock.
We can use two pairs of contacts connected in series.
And now we have an inactive clock reduced by about 140dB.
But in this design, if two clocks are installed, crosstalk effects occur.
This is due to the fact that two signals enter to the Clock Buffer (LMK1C1104PWR).
The first one is the active clock and the second one is the inactive clock
reduced by about 70dB (by relay G6K-2F-RF-DC5 - this is what the documentation says).
See isolation for 25MHz is about 70dB:
The same can be seen in the signal spectrum:
But when we take out the inactive clock from PCB we have:
As you can see, 70dB isolation is not enough...
We can improve this by using one relay per clock.
We can use two pairs of contacts connected in series.
And now we have an inactive clock reduced by about 140dB.
I made a new version of the clock board for 22/24MHz clocks:
Signal spectrum looks ok:
Signal spectrum looks ok:
Goes to show the importance of measurements.
While the oscillator phase noise may be slightly higher for a short period after power-on I would question the need for "always-on" approach. Most have music only on one clock family so the need to change between clock families is not frequent. Unless the oscillator is on 24x7 there will anyhow be a period of elevated phase noise at power-on. But most importantly has the audibility of this elevated phase noise at power-on been validated in studies or controlled listening tests? The crosstalk noise of 2 clocks with single relay was very likely more audible than the elevated power-on phase noise. So if nobody was able to hear the crosstalk then how would they hear the phase noise?
Hi Piotr,
Thank you for the contribution 🙂
As to your findings, I was always aware that there could be some crosstalk with the single relay system. However, I did testing with only one clock or with two clocks installed on the clock board. No audible difference was found here between the two cases, except as described in post #144. Also, part of the reason for always having two clocks powered on and enabled was for compatibility with Andrea Mori FIFO and or USB boards, which require both clocks to be running at all times.
Regarding leaving the clocks powered on, the effects of not doing so is audible on my system when using S-cut quartz crystal oscillators, such as those from Iancanada, Andrea Mori, and Acko Labs. Similar effects were found in Crystek and Accusilicon clocks here a few years ago. Mostly what is affected with Marcel's RTZ dac and Acko clocks is sound stage imaging. However, if there are bigger problems with a dac, or with a system, and or with a room then its hard to say what may or may not be audible.
EDIT: Another thought about crosstalk. In this case we are interested in clock edge timing. If crosstalk between clocks were to modulate a little ripple on the top of the clock waveform, it would of no consequence. Only clock edges at the switching threshold of the reclocker matter. Thus, looking at a spectral view may be misleading. It isn't like all those different frequencies are independently clocking the dac. In one model for thinking about it there has to be a collision exactly at a rising clock edge, and it has to be significant at least as compared to the inherent jitter of the clocks at low offset frequencies to be audible. Of course if the crosstalk gets bad enough then noise may cause more than small, periodic clock edge perturbations.
Thank you for the contribution 🙂
As to your findings, I was always aware that there could be some crosstalk with the single relay system. However, I did testing with only one clock or with two clocks installed on the clock board. No audible difference was found here between the two cases, except as described in post #144. Also, part of the reason for always having two clocks powered on and enabled was for compatibility with Andrea Mori FIFO and or USB boards, which require both clocks to be running at all times.
Regarding leaving the clocks powered on, the effects of not doing so is audible on my system when using S-cut quartz crystal oscillators, such as those from Iancanada, Andrea Mori, and Acko Labs. Similar effects were found in Crystek and Accusilicon clocks here a few years ago. Mostly what is affected with Marcel's RTZ dac and Acko clocks is sound stage imaging. However, if there are bigger problems with a dac, or with a system, and or with a room then its hard to say what may or may not be audible.
EDIT: Another thought about crosstalk. In this case we are interested in clock edge timing. If crosstalk between clocks were to modulate a little ripple on the top of the clock waveform, it would of no consequence. Only clock edges at the switching threshold of the reclocker matter. Thus, looking at a spectral view may be misleading. It isn't like all those different frequencies are independently clocking the dac. In one model for thinking about it there has to be a collision exactly at a rising clock edge, and it has to be significant at least as compared to the inherent jitter of the clocks at low offset frequencies to be audible. Of course if the crosstalk gets bad enough then noise may cause more than small, periodic clock edge perturbations.
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I have actually seen the impact of similar but lower-level clock crosstalk at DAC output measurement. There was lots of low-level hash around the fundamental similar to what higher jitter clock can cause. Probably not audible, but if not, then much lower phase noise could hardly be audible.
Empirical evidence here is that with one or two Iancanada clocks, imaging was the same. There was some anomaly in the center image between the speakers where, for example, vocals were a bit blurred and recessed towards the back of the sound stage.
When it came to using sine wave oscillators such as from Acko Labs I had to design an improved squaring circuit (Iancanada clocks have internal squaring). My squaring board replaces most of the functionality of the clock board, except for the PLL to drive the USB board. That fixed the center image, and also improved soundstage depth. The squaring board uses a single relay, yet there is no difference in imaging if only one or if both oscillators are connected.
Also despite the anomaly with Iancanda clocks, I still recommend them if cost is a limiting factor since they sound soooo much better than Crystek, Accusilicon, and or NDK SDA. Eventually someone besides me will probably try them and describe the difference.
When it came to using sine wave oscillators such as from Acko Labs I had to design an improved squaring circuit (Iancanada clocks have internal squaring). My squaring board replaces most of the functionality of the clock board, except for the PLL to drive the USB board. That fixed the center image, and also improved soundstage depth. The squaring board uses a single relay, yet there is no difference in imaging if only one or if both oscillators are connected.
Also despite the anomaly with Iancanda clocks, I still recommend them if cost is a limiting factor since they sound soooo much better than Crystek, Accusilicon, and or NDK SDA. Eventually someone besides me will probably try them and describe the difference.
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Just a note about the clock board @PJotr25 posted in #232, I sent him a PM about a possible phase noise problem and or other possible problems related to layout (don't know if anyone else noticed). Only point is I would suggest to wait to see how he responds before people go out and start ordering PCBs.
Also, I would remind folks of the document @dddac attached to post #103 which details the limitations of spectral analysis for phase noise assessment.
Also, I would remind folks of the document @dddac attached to post #103 which details the limitations of spectral analysis for phase noise assessment.
There are always many ways to solve problems...
We often talk about small things and forget about big issues.
Here the big issue is mixing two clocks.
I showed the solution...
We don't talk about it.
Measurements are used to draw conclusions, if we can do that, they help us...
Okay. I will share what I think is a problem here. Its this:
This is the output buffer layout from the board in #232. In the lower left corner is the ground pin off the buffer chip. It has no low impedance path back to the chip's bypass cap. I know from experience that this type of problem can be audible, probably due to jitter associated with ground bounce. I know it from listening tests since almost nobody including me has close-in phase noise measurement equipment. For anyone familiar with Marcel's RTZ dac layout, its obvious Marcel thought about the bypass current loop path for his shift registers. In most cases its okay to use close-by vias as shown in the buffer documentation like this:
However, that's not as good IMHO and IME as what I like to do, which I believe is in agreement with @ThorstenL, and which is to keep bypass current on surface under the chip, without looping through vias. IIRC, @KSTR also strongly agreed with the surface fill under the chip approach, in that case for opamps, in another old thread about bypass caps started by gentlevoice (which I don't have a link to right now since the change in forum software some time ago broke all the existing links that I have a record of). I would say its probably even more important when using linear bypass caps with more self-inductance instead of tiny X7R caps. Here is an example of that type of routing concept, although it happens to be with a different chip:
Now back to the subject of "mixing" of clocks. Again, experience shows it to be a non-issue probably because small amplitude noise between clock edges is not important. Even if there is added edge timing jitter in the time domain it has little effect on sound unless its close-in. Otherwise it mostly only affects the fixed, low-level audio noise floor and tends to be inaudible. IOW, its trying to measure the wrong thing. However, its perfectly okay to use more relays than needed if someone wants to do that.
So, moving along here, this is how I see it: Someone has a spectrum analyzer but doesn't have close-in phase noise measurement equipment and also doesn't do listening tests. What they do is measure using whatever instruments they have and assume that measures everything that can possibly matter, and furthermore that whatever is measured must matter if it doesn't look good to the eye on a screen. IME that type of assumption is a common mistake in audio design.
Again, I base my opinions on listening tests and experience with different dac board layouts. I will let Piotr have the last word on the matter if he wishes.
This is the output buffer layout from the board in #232. In the lower left corner is the ground pin off the buffer chip. It has no low impedance path back to the chip's bypass cap. I know from experience that this type of problem can be audible, probably due to jitter associated with ground bounce. I know it from listening tests since almost nobody including me has close-in phase noise measurement equipment. For anyone familiar with Marcel's RTZ dac layout, its obvious Marcel thought about the bypass current loop path for his shift registers. In most cases its okay to use close-by vias as shown in the buffer documentation like this:
However, that's not as good IMHO and IME as what I like to do, which I believe is in agreement with @ThorstenL, and which is to keep bypass current on surface under the chip, without looping through vias. IIRC, @KSTR also strongly agreed with the surface fill under the chip approach, in that case for opamps, in another old thread about bypass caps started by gentlevoice (which I don't have a link to right now since the change in forum software some time ago broke all the existing links that I have a record of). I would say its probably even more important when using linear bypass caps with more self-inductance instead of tiny X7R caps. Here is an example of that type of routing concept, although it happens to be with a different chip:
Now back to the subject of "mixing" of clocks. Again, experience shows it to be a non-issue probably because small amplitude noise between clock edges is not important. Even if there is added edge timing jitter in the time domain it has little effect on sound unless its close-in. Otherwise it mostly only affects the fixed, low-level audio noise floor and tends to be inaudible. IOW, its trying to measure the wrong thing. However, its perfectly okay to use more relays than needed if someone wants to do that.
So, moving along here, this is how I see it: Someone has a spectrum analyzer but doesn't have close-in phase noise measurement equipment and also doesn't do listening tests. What they do is measure using whatever instruments they have and assume that measures everything that can possibly matter, and furthermore that whatever is measured must matter if it doesn't look good to the eye on a screen. IME that type of assumption is a common mistake in audio design.
Again, I base my opinions on listening tests and experience with different dac board layouts. I will let Piotr have the last word on the matter if he wishes.
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