Regarding my distant recollection regarding KSTR and opamp bypass, think this was the thread:
https://www.diyaudio.com/community/...apacitor-simulation-model.382329/post-6944576
https://www.diyaudio.com/community/...apacitor-simulation-model.382329/post-6944464
Anyway seems under-the-chip byass routing is not a new idea.
https://www.diyaudio.com/community/...apacitor-simulation-model.382329/post-6944576
https://www.diyaudio.com/community/...apacitor-simulation-model.382329/post-6944464
Anyway seems under-the-chip byass routing is not a new idea.
I think you are right.
Any reason to not place the decoupling directly under the IC?
Seeing this:
Why not place a pair of VIA's at each Vcc or Vss pad into the Vcc & Vss plane (plus Vss plane fill on top) and then the decoupling capacitor below the IC with pads connecting to each set Vias (only).
Image planes for Vss and Vcc are pretty much de rigueur for anything above a few MHz.
A pretty decent decoupling group can be placed below the IC. How about 4 X 1uF X7R in 00805 or 1206 (whatever fits - the benefit of making the capacitor physically smaller than pin distance is non-extant), or C0G if we must.
For illustration the PCB, both sides of the original iFi ZenDAC (PCB design under my supervision):
Top side has all "tall" components and every decoupling capacitor, power islands for some sections can also be seen.
Bottom side is IC's and directly related signal routing. PCB is 4-Layer.
The PCB obviously passes twice through reflow, in practice this has no reliability implications in mass production, price difference is nominal.
Thor
In the time domain that would more or less seem like saying that spur frequencies that change clock edge timing with some periodicity, such as by perhaps by summing to change risetime slope in some repeating pattern over multiple cycles, and when such periodicity is not notched out by the FIR filter structure, then the periodic pattern could be equivalent to (an alias of) some pattern in the audio band (where a timing error is then approximately equivalent to an amplitude error). Something like that. Maybe there is a better way of putting it?
Just trying to see if there is a way to help build intuition in the time domain view.
Just trying to see if there is a way to help build intuition in the time domain view.
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Yep, I would agree that this layout is quite non-ideal. The return current will have to go left, circle around R4, switch to the other side at the three vias above R5, and finally switch sides at the via block right of C7 which seems to be the decoupling cap. Further, the connecting trace to C7 is pretty narrow, increasing inductance.
This is the output buffer layout from the board in #232. In the lower left corner is the ground pin off the buffer chip. It has no low impedance path back to the chip's bypass cap.
The fix would be easy: Place C7 right below IC2 so that it bridges over that vertical trace, and use wide traces (I most often do not use trace "wires" but simple rectangular fills combined to get wide traces).
And of course, as mentioned in another thread, place GND stitching vias everywhere and notably along any longer traces.
The basic idea is to think of the PCB as one solid copper block, all layers being initially GND and all layers connected together with tons of stitching vias. It's not uncommon to have hundreds of them, sometimes even thousands.
And, use as many layers as you can afford (not less than four, at any rate) and make the board as thin as possible.
I find it quite odd that so much time is wasted on speculation. Seems more like whataboutism to divert attention when a fault was found in the original design. While the proposed new layout may not be ideal it has not been proven to be an issue either. Easiest fix is to follow LMK1C1104 datasheet and drop a few vias to GND planes at IC GND pin.
Its quite an assumption to make about other people's motivation to refer to discussion of a real problem as a diversion. There was no diversion and no need for one, there was just a lot freaking out by a few people looking at a spectrum without realizing there was no audible problem shown by it. It was a big nothing burger.
Or to put it in other terms, Marcel seemed to sum it up in his own way:
Or to put it in other terms, Marcel seemed to sum it up in his own way:
Instead of making unsubstantiated claims maybe you should show some measurements to convince us.
I described listening test results already, both with a single clock and with two clocks. That is a type of measurement, one very much suited to performance of an audio device intended for human listening. Doesn't matter what people with the ASR mentality want to believe.
Also I accept Marcel's analysis which he described as "fortunate," and which coming from Marcel I am sure is based on the math of the harmonics of both clock frequencies.
Also I accept Marcel's analysis which he described as "fortunate," and which coming from Marcel I am sure is based on the math of the harmonics of both clock frequencies.
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People with audiophile mentality would claim the reason for you not hearing a difference is that your system may not be revealing enough. People with ASR mentality would claim that your listening test lacks controls so it is an evidence-free claim anyhow.
IME people at ASR don't always claim a lack of controls once they find out what kind of controls you use 😉
That is after having tried to explain it in this forum before only to have it be rejected by certain people who don't want to understand it. I will leave it at that.
That is after having tried to explain it in this forum before only to have it be rejected by certain people who don't want to understand it. I will leave it at that.
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Apparently my earlier post has caused some misunderstandings. Apologies for that.
Spurious tones on the clock will impact the performance of sigma-delta DACs (such as DSD DACs) by mixing out-of-band quantization noise into the audio band, and as always, quantization noise is not simple additive noise. It's really a weird kind of intermodulation distortion that often resembles noise, but is actually signal-dependent in very complicated ways.
You see that most clearly around half the sample rate (and its odd multiples), where depending on the sigma-delta modulator algorithm, the quantization noise often degenerates into tones or narrow noise bumps that get frequency-modulated by the desired signal. It's very fortunate that because of their frequencies, the biggest spurious tones we discuss here at least won't mix that into the audio band.
Regarding
That's true of course, but assuming that the clock buffer has a clean supply, the signal PJotr25 measured in post #231 had already passed through a slicer that clips off such ripples, namely the clock buffer. That is, it seems that the dirty spectrum is really due to shifted edges.
In any case, if anyone wants the best of both worlds, take PJotr25's design improvement and combine it with all layout improvements one can think of.
Spurious tones on the clock will impact the performance of sigma-delta DACs (such as DSD DACs) by mixing out-of-band quantization noise into the audio band, and as always, quantization noise is not simple additive noise. It's really a weird kind of intermodulation distortion that often resembles noise, but is actually signal-dependent in very complicated ways.
You see that most clearly around half the sample rate (and its odd multiples), where depending on the sigma-delta modulator algorithm, the quantization noise often degenerates into tones or narrow noise bumps that get frequency-modulated by the desired signal. It's very fortunate that because of their frequencies, the biggest spurious tones we discuss here at least won't mix that into the audio band.
Regarding
That's true of course, but assuming that the clock buffer has a clean supply, the signal PJotr25 measured in post #231 had already passed through a slicer that clips off such ripples, namely the clock buffer. That is, it seems that the dirty spectrum is really due to shifted edges.
In any case, if anyone wants the best of both worlds, take PJotr25's design improvement and combine it with all layout improvements one can think of.
In that case I would suggest Piotr take a measurement after the reclocker. That's what is actually going into the dac. In my system at the moment the MCLK signal is going through both inverters on the reclocker board because the propagation delay through PCM2DSD seems to be dependent on the incoming PCM sample rate. For 24/192 it may be that no upsampling is done, only modulation to DSD256. That might have a shorter delay than upsampled 16/44. Thus I made a temporary timing adjustment on the reclocker for convenience until I can delay the USB board clock sufficiently.
One thing I am not sure about is that the output buffer has gain, but not infinite gain. It may amplify some low level frequencies to some degree but not necessarily to clipping. If it amplifies some frequencies to much less than the switching threshold of the reclocker, it might be kind of hard to say at this point how much edges might be shifted to a significant degree. What I find somewhat perplexing is that no audible difference is found between one clock and two clocks, with soundstage staying quite intact. There needs to be some way to make sense out of the various observations that is not unduly presumptive of listening errors.
Also, it could be there is some added noise in the audio band due to using only one relay. However, if its inaudible then who cares? Also, because this is a DSD dac it probably has worse SINAD than a ESS dac optimized for best measurements. Who cares about that if your dac sounds better to humans? Yet by some reasoning we should just change it to an ESS dac because it will measure better. Personally, I don't necessarily agree with the need to do that just to get better numbers.
One thing I am not sure about is that the output buffer has gain, but not infinite gain. It may amplify some low level frequencies to some degree but not necessarily to clipping. If it amplifies some frequencies to much less than the switching threshold of the reclocker, it might be kind of hard to say at this point how much edges might be shifted to a significant degree. What I find somewhat perplexing is that no audible difference is found between one clock and two clocks, with soundstage staying quite intact. There needs to be some way to make sense out of the various observations that is not unduly presumptive of listening errors.
Also, it could be there is some added noise in the audio band due to using only one relay. However, if its inaudible then who cares? Also, because this is a DSD dac it probably has worse SINAD than a ESS dac optimized for best measurements. Who cares about that if your dac sounds better to humans? Yet by some reasoning we should just change it to an ESS dac because it will measure better. Personally, I don't necessarily agree with the need to do that just to get better numbers.
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Thanks for this excellent example, notably the ton's of stitching vias and via fences along the outer edges and around traces. My boards are all copper+solderstop-covered vias and thus invisible.
Also good info on the double reflow process. Up to now I've only used wave soldering for (larger) bottom side SMT components where the parts need to be glued to the board first.
I would guess when the process parameters are correct one does not need the glue on the bottom-side components for the second pass, right?
Actually, a new and improved clock board would be fine with me. As long as its as good or better than my original clock board in every way that can affect audibility then its an advancement for everyone. My concern would be if a new clock board was touted as being an improvement when actually it did more harm than good because of things like layout issues. Just because layout problems can in some cases be harder to measure the effects of doesn't mean they don't matter. It also doesn't mean they matter less than clock mixing (which still remains of questionable audibility providing recommendations in post #144 are followed).
Also, one of the things that Piotr did that is probably fine for a new clock board omit support for clock division (if people don't want to use Accusilicon clocks), and omit support for Andre Mori FIFO and or USB boards (since people usually use Andrea's clocks for that anyway).
Before proceeding though, there are some things it would be good to know from Piotr such as where he measured, and how the clock board was configured. Was it configured according to post #144 recommendations (because there is a reason a link to that particular post is given in the first post of the thread)? Was the measurement taken from some particular connector on the clock board? Was it taken from after the reclocker? Without knowing the measurement conditions, some measurement problem may have occurred like sometimes happens in ASR measurements. At this point we don't know. Its still quite possible the relays are being wrongly blamed when the real issue is that the clock board was not configured appropriately by the user.
Please see the NOTE at: https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/post-7729060
Regarding human bias in this case, very few people have close-in phase noise measurement equipment because its expensive. OTOH, RF spectrum analyzers are pretty common. We should remain aware of the human tendency to over-focus on certain parameters simply because those parameters happen to be most convenient to measure.
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Thank you for the flowers.
One should consider that this is for a 2.6 USD in 1ku 113dB SNR DAC chip. I often cringe when I see much higher grade IC's in much poorer layouts.
Correct. We all now use ROHS solder paste which is "phase-change" if I remember the term right.
After applying the past via stencil and machine placing components, the paste holds the components in place for minor force or tilted boards.
After the first reflow, the solder paste changes so it needs a temperature notably higher than the official reflow temperature and reflow ovens have very tight temperature and process control these days. It's a whole science in itself. But even low end Chinese PCBA houses seem to master it all right.
You can see the results of mass production using such processes on the board pictures. Looks pukka enough to me, innit?
Thor
You have on many occasions promoted the phase noise measurements I used here: https://www.diyaudio.com/community/threads/phase-noise-in-ds-dacs.387862/. Most recently at ASR of all places: https://www.audiosciencereview.com/...ibility-of-dac-phase-noise.56660/post-2068050. It may come as a surprise to you but Marcel's RTZ dac is just an ok performer in such measurement. Better than dacs using PLL or synthesizer clocks (e.g. RME ADI-2 or SMSL). But with identical clocking my AK4493 or ES9039Q2M dacs have about 20dB lower noise skirts. So well implemented AKM & ESS dacs have better measurements even regarding phase noise. And they sound just as good (or even better).
BTW your thread (link above) at ASR is a disturbing read. You give the impression that your RTZ dac is your own build. No mention of Marcel or the thread here at diyaudio.
My particular RTZ dac is system which consists of several boards, power supplies, transformers, output stage, etc. Some of the boards in the system come from various sources and some are of my own design. Only the system design as a whole gives the overall performance. And, yes, as in your example its possible for Marcel's RTZ dac to perform poorly if implemented poorly.
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As before instead of making unsubstantiated claims why not show us how well your RTZ dac performs in phase noise measurement.
Attached to post #103 https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/post-7709201
Is a document on phase noise measurement. Section 2.5 is is: "Challenges/limitation of the spectrum analyzer method"
I would suggest for people to read it before relying too much on that method.
Is a document on phase noise measurement. Section 2.5 is is: "Challenges/limitation of the spectrum analyzer method"
I would suggest for people to read it before relying too much on that method.