Fast MosFET amp with LT1223 opamp front end

I have 1st quick test results.

1) Let's start with bad news:

With LT1223 op-amp, amp works fine only under certain level of idle current (for the output devices).
E.g. with idle current under 50mA, it produces nice sinus and square waves
on the oscilloscope.

However - if idle current is increased (E.g. to simmed 150mA), sinus waves
produced are 'thick'. There is some oscillation on them.
Or, even with low idle current, if certain level of output level is reached,
the bottom of the sinus waves will be thicker, and eventually, at higher
output levels, the whole sinus wave is thicker (oscillations).
Observed rise time on square waves is very good: 500ns.

2) Now better news:
I tried LF356 op-amp (slew rate only 12V/us) - even though in the sim it didn't work that well
(sim was specifacally targeted for LT1223), and voila - amp is very stable, produces perfect
square and sinus waves with either low or high idle current settings (tried up to 150mA).
And, what's even more strange - the observed slew rate is almost unchanged, still in 500 - 600ns

With Vpp reaching almost 60V (without the load), rise time was 580ns (34kHz square waves),
which translates to over 100V/us, and it's the highest slew rate I ever saw on any amp I built,
including my build of Groner amp, which in the sim was showing 240V/us.
I had to remove Zobel RC for these tests, as the resistor was about to burn.

With 8 Ohm load I couldn't go that high with output levels, but at lower Vpp values, rise time
was still 500 - 600ns.
All the screenshots with Vpp in lower ranges, are done with 8 Ohm load.

So to me, as far as LF356 goes, it all looks good.

Will continue these tests in 2 directions:
a) with other op-amps (E.g. LT1056)
b) with original LT1223 - will try to tweak the compensation to get rid of the oscillation.
But this seems kind of pointless, unless this op-amp can deliver even higher bandwidth.
If it still gonna reach rise time not better than 400-500ns, it's not worth to bother.

With both op-amps, output DC offset is 1.5 mV (with C8 populated; initially I skipped it, but without it offset was 200mV).

It seems to me that in this case, LTSpice sim is not really a match for the real world build..
LF356 wasn't supposed to work at all with this schematic 'as is'...

test_bed1.jpg


test_bed2.jpg


square_9v_34khz_500ns.jpg


square_68khz_600ns.jpg


square_58V-580ns.jpg


good_sinus.jpg
 
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I like the ad-hoc heatsink mounting system. Very handy for bench testing purposes. I've used wide polyimide tape for insulating power transistors, seems to work OK (so far). My particular application was for a class A headphone amplifier & the quiescent power dissipation is low, about 1.5 watts/device. But the tape is used for anchoring parts during solder reflow so.....I see no reason why it can't be used for higher-power amplifiers as well. If it goes into failure you have some much bigger problems to worry about.....

I guess I'm not too surprised that your sims and bench testing don't agree. Using the opamp's power supply pins as outputs may not be covered very well by the device model. As evidenced by your results using the LF356. You win some you lose some?
 
Based on some debug experience I had on a design I worked on a (very) long time back, I'm wondering if some of these problems are due to parasitic inductance. In my case it was excessively-long connections to the output devices' collectors. The circuit behavior was contrary to everything I expected, and resisted all efforts to fix it -- until I added some bypass caps right at the output collectors. The problem only showed up when I was driving a load and that is what finally clued me in to what was going on. V = L *dI/dt so for a non-terminated output di/dt was small. It blew up when dI/dt got bigger, i.e., when driving a real load. The voltage transients on the collectors were high enough to modulate their output -- maybe capacitive, maybe messing with device beta via base-width modulation (a.k.a. Va) -- but once I figured out how to fix the problem I declared victory regardless of the actual mechanism and moved on.

Parasitics introduced by the PCB layout won't appear on a SPICE netlist, unless the designer puts them there.

So, one relevant question is: how does the amplifier behave with NO load? Got a few-uH inductor in series with the output? It would help reduce dI/dt, just something else to use to eke out the nature of the problem
 
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So, one relevant question is: how does the amplifier behave with NO load?
Got a few-uH inductor in series with the output? It would help reduce dI/dt, just something else to use to eke out the nature of the problem

So far from my tests, the amp behaves the same with or without the load. Which I guess is good.
Well, so far it was purely resistive load, I'll proceed with more testing with capacitive loads..
I could try the inductor, but I would prefer to make this amp stable without it.
In the actual build, to play music, I will have RL network, but for the sim and testing I usually skip them.
If amp is not stable without RL, I'm not interested in it...
 
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Experimenting/debugging a live circuit is a great way to go. My amp definitely did not behave as predicted, in one case it was the result of a stupid decision to leave out a couple of critical decoupling caps in circuitry used to bias the input cascodes, in the other the sims were not accurate enough for me to properly compensate the amplifier.

I have electronic offset protection using speaker relays as well which has thrown me some interesting curves not seen in sims, not on the bench with lab supplies, and only when I tried to use it. (Now "mostly" fixed) The amp in question is new.
 
I learned the hard way that zeners are not always the low impedance devices we think they are, bypassing them is definitely a good idea. (At least 10uF perhaps shunted with a 0.1uF ceramic cap as well. A very small resistor between the bases of Q3 and Q4 to the respective zener is helpful as well. (Try 10 - 47 ohms)

Consider adding miller compensation on Q1 and Q2. Experiment with the value of C7 as well.

Might also reduce the value of C6 or increase the value of R30, some tiny number driving devices may not like the low input impedance at high frequencies - with my luck I would undoubtedly have something that would complain.

I made some similar mistakes in mine which required minor reworks to fix.

Your overall design is sound. I used the Alexander configuration in a line of commercial MI amps I designed 20+ years ago, all was great until production when the purchasing agent subbed the wrong transistor hfe grade for Q3 and Q4 and the first 100 or so that came off the line oscillated. It took me a couple of days to figure that out, and of course I got blamed for the mistake. I made two running changes to fix the problem - added local bypass on +/-15V rails used as reference and series base resistors.
 
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Late to the party.
Proof of concept. I leave the ideal voltage sources in for now. Also please ignore the potential DC offset issue for now.

I would recommend this approach to get 100% stable.
The opamp gets its NFB by its own. Thus, opamp should be unconditional stable.
The output stage is compensated through R1 and C3. (You could ignore R4.)
It works as current feedback. The low impedance output of the opamp works as the negative input on current feedback opamp, the current on R1 will be mirrored back to the VAS.
1743260966545.png
 
Tried LT1056 - my favorite op-amp, used in many of the amps I've built so far.
Here it doesn't work at all. Total failure.

Then I tried TLE 2081 (45V/us) op-amp.
Works like a champ. Everything stable, squares are fine, with little bit over 600ns rise time (under load), so pretty fast.

Testing will continue...

20250329_154519_HDR.jpg

20250329_154523_HDR.jpg
 
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