F8

Does anyone know about power on/off thumps in the F8? In my simulations, I can control it, but not eliminate about +4V thump at power on, probably audible only low frequency.
 

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I used an oversimplified power supply simulation. The rectifier and capacitors are used as a simplistic model for the voltage decay when the power is turned off. The rise time Tr is a simplistic ramp for the power on voltage, including effects due to the CL-60 inrush current limiter on the transformer primaries.
 

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Maybe showing more plots will help.


  1. The top plots are Vd+,the output from the PWL voltage source, and V+ the rectified/filtered voltage.
  2. The second plots are the FET currents Q2, the IRFP240 and Q1, the SemiSouth R100.
  3. The third plot is the output voltage.
 

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I really mean their kind of writing!

And I confess that I feel like Sherlock Holmes looking at the partial information the pictures give.
A kind of crossword puzzle for the brain, making me really nervous.
Like the Christmas gifts on the wardrobe I wanted to look at as a child, judging from shape, what it could be.
 
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