I think this is music to anyone looking at using these chips in DIY projects ears, thanks for the clarification Dustin, I think you guys have just gained a new market segment, it may not be huge, but most certainly fanatical
Definitely, but really it needs to be more than just schematics we can make public. Those have been public for a long time.
It is really the registers and such that the DIY folks really need now.
It is really the registers and such that the DIY folks really need now.
yep, last step towards unleashing the power of this device, and it really is quite a lot of power there. particularly towards integration/automation. yeah like I said, as far as the DS goes thats the most comprehensively covered area. I guess we'll see where this goes, perhaps now that it can be requested by anyone who asks nicely it will effectively be made 'public' anyway.
Russ, I'm not sure where the 'public' Buffalo II DAC schematics are. I don't see them on the TPA site.
When did I say there were any?
I did say that there were schematics (mine and others) but not of the Buf II.
I did say that there were schematics (mine and others) but not of the Buf II.
Latest version of datasheet is 1.2.
According to the change log the change from 1.1 is only to correct an error in calculating the sample rate. But if you already figured that out then you don't need the new datasheet.
According to the change log the change from 1.1 is only to correct an error in calculating the sample rate. But if you already figured that out then you don't need the new datasheet.
ahh you are correct, its from 1 to 1.1 that was the big change (as you would expect). I had all three open (but I only remember ever getting 2) and only went off the size of the PDF file for amount of changes, late night lazy posting.
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Issue with Sabre I2S Interface?
So far I have collected 6 reports regarding having issues with the I2S interface of the Sabre DAC:
1. Hiface Evo
2. TPA USB board based on the PCM2707 chip
3. Musiland MINI, based on Spartan FPGA
4. Teralink-X2 based on TENOR TE7022L and 1ppm TCXO
5. AudioGD ESS DAC
6. "Manufacturer X" converting I2S into SPDIF before feeding the DAC
More info here: Musiland MINI I2S to Buffalo II DAC H I F I D U I N O
The workaround seems to be increasing the DPLL bandwidth, although there is a report of having problems even at MAX dpll bandwidth. The other solution is to use the spdif interface which works fine at lowest dpll bandwidth.
It would be nice to get to the bottom of this. Any ideas?
So far I have collected 6 reports regarding having issues with the I2S interface of the Sabre DAC:
1. Hiface Evo
2. TPA USB board based on the PCM2707 chip
3. Musiland MINI, based on Spartan FPGA
4. Teralink-X2 based on TENOR TE7022L and 1ppm TCXO
5. AudioGD ESS DAC
6. "Manufacturer X" converting I2S into SPDIF before feeding the DAC
More info here: Musiland MINI I2S to Buffalo II DAC H I F I D U I N O
The workaround seems to be increasing the DPLL bandwidth, although there is a report of having problems even at MAX dpll bandwidth. The other solution is to use the spdif interface which works fine at lowest dpll bandwidth.
It would be nice to get to the bottom of this. Any ideas?
So far I have collected 6 reports regarding having issues with the I2S interface of the Sabre DAC:
1. Hiface Evo
2. TPA USB board based on the PCM2707 chip
3. Musiland MINI, based on Spartan FPGA
4. Teralink-X2 based on TENOR TE7022L and 1ppm TCXO
5. AudioGD ESS DAC
6. "Manufacturer X" converting I2S into SPDIF before feeding the DAC
More info here: Musiland MINI I2S to Buffalo II DAC H I F I D U I N O
The workaround seems to be increasing the DPLL bandwidth, although there is a report of having problems even at MAX dpll bandwidth. The other solution is to use the spdif interface which works fine at lowest dpll bandwidth.
It would be nice to get to the bottom of this. Any ideas?
With the Sabre32 DAC I can run the minimum DPLL bandwidth with 192k/24bit on SPDIF and 352.8k/32bit on I2S.
I do not know what "the" problem are, but I use the Sabre32 in Sabre32 modus and pinout.
Uses the SPDIF mux on DATA6, 7 and 8.
Uses the I2S with SPDIF disabled on DATA2, 3, 4 and 5.
Uses a 98.304MHz clock with less than 0.5ps jitter.
Uses JFET regulators etc...
Only the "000 No bandwidth" setting are not working, but I am not sure if it should work at the input rates I use or at all for that matter???
I can use all internal settings like normal/50k/60k/70k/slow/fast/OSF disable/enabled / quantizer 6/7/8/9bit etc...
Thus I would not expect that there are any internal causes to the problems as I have no DPLL issues with any internal settings.
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I honestly have never had any trouble with any clean I2S source keeping a lock on the lowest DPLL setting at any bit depth or sample rate. You do have to be very careful about the signal routing and GND returns. Even with the PCM2707 I don't have any issues.
I am not saying there may not be some issue, but if there it it is likely not the fault of the chip. More likely to find the problem looking at more basic design concerns.
Having thousands of working DACs out there I have only heard a handful of issue regarding I2S, and most of those were solved by simply using better routing and paying attention to GND return.
So not sure where you want to take the discussion. From a DIY perspective it is easy enough to use what ever DPLL BW you see fit.
I am not saying there may not be some issue, but if there it it is likely not the fault of the chip. More likely to find the problem looking at more basic design concerns.
Having thousands of working DACs out there I have only heard a handful of issue regarding I2S, and most of those were solved by simply using better routing and paying attention to GND return.
So not sure where you want to take the discussion. From a DIY perspective it is easy enough to use what ever DPLL BW you see fit.
Is this a problem with synchronisation/timing issues between he I2S lines - these lines need to be the same length?. I seem to remember somewhere that the Sabre DAC is particularly sensitive to this mis-timing!
Hi Russ,
Just curiosity from a "technical mind" as more reports keep popping up, nothing "evil" 🙂
Just curiosity from a "technical mind" as more reports keep popping up, nothing "evil" 🙂
With the Sabre32 DAC I can run the minimum DPLL bandwidth with 192k/24bit on SPDIF and 352.8k/32bit on I2S.
I do not know what "the" problem are, but I use the Sabre32 in Sabre32 modus and pinout.
Uses the SPDIF mux on DATA6, 7 and 8.
Uses the I2S with SPDIF disabled on DATA2, 3, 4 and 5.
Uses a 98.304MHz clock with less than 0.5ps jitter.
Uses JFET regulators etc...
...
RayCtech, thanks for sharing.
Based on your description, you can connect 3 spdif sources and 1 i2s source and select them in s/w? That's pretty cool.
Hi Russ,
Just curiosity from a "technical mind" as more reports keep popping up, nothing "evil" 🙂
No I would never think such. But I am just saying it is definitely not a common problem as far as I am aware.
try 8 spdif and 1 i2s, but I guess you can only have 6 and 1. but as I was telling RayCtech, you cannot switch i2s, anything playing on i2s will continue to play underneath any spdif channel you select, obviously you just stop it, but the connection is still there
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