Zoran,
Basically the part comes up in I2S with the 4 data input lines associated as four stereo pairs.
Therefore if you parallel the 4 data lines and the 4 positive and 4 negative outputs you basically end up with a stereo unit.
You can then use the part in either voltage mode or current mode depending on the output circuit you devise.
Thanks
Gordon
Basically the part comes up in I2S with the 4 data input lines associated as four stereo pairs.
Therefore if you parallel the 4 data lines and the 4 positive and 4 negative outputs you basically end up with a stereo unit.
You can then use the part in either voltage mode or current mode depending on the output circuit you devise.
Thanks
Gordon
Thanks...
I check the datas again
not much about I2S input...
*
so I persume next:
(because, dacs output nested on power supply pins marked L/R)
*
output (every dac has differential outs...)
DAC 1,3,5,7 = Left
DAC 2,4,6,8 = Right
*
TRUE or FALSE ?
*
*
input I2S (UP to 24bit) or DSD
*
pin
51 GND
52 dsd data8
53 dsd data7
54 dsd data6
55 I2S data dac7/dac8 dsd data5
56 I2S data dac5/dac6 dsd data4
57 I2S data dac3/dac4 dsd data3
58 I2S data dac1/dac2 dsd data2
59 I2S L/R CLK dsd data1
60 I2S BCLK dsd bit clock
*
TRUE or FALSE ?
*
All I2S data pins shoul be connect together ?
*
thanks
I check the datas again
not much about I2S input...
*
so I persume next:
(because, dacs output nested on power supply pins marked L/R)
*
output (every dac has differential outs...)
DAC 1,3,5,7 = Left
DAC 2,4,6,8 = Right
*
TRUE or FALSE ?
*
*
input I2S (UP to 24bit) or DSD
*
pin
51 GND
52 dsd data8
53 dsd data7
54 dsd data6
55 I2S data dac7/dac8 dsd data5
56 I2S data dac5/dac6 dsd data4
57 I2S data dac3/dac4 dsd data3
58 I2S data dac1/dac2 dsd data2
59 I2S L/R CLK dsd data1
60 I2S BCLK dsd bit clock
*
TRUE or FALSE ?
*
All I2S data pins shoul be connect together ?
*
thanks
any of you guys thought about adding the ESS chip to the end of the DCX unit ?
would it be easy to achieve?
would it be easy to achieve?
Russ White said:
Can you please explain why the Buffalo board will not lock onto signals greater than 48k? I have your made up board with Ivy.
You advised in a post that the Notch Delay Switch should be Low. However, I can hear distortion when so set. have I misunderstood?
Fred
Anybody had the time to test the Sabre DAC with a transformer replacing the i/v stage yet? If so, please post a schematic and indicate what type of tranny you have used.
fmak said:
FMAK, I think you are confusing the buffalo for the PCM2707 board we carry. The PCM2707 USB moduel is not capable of more than 48khz.
The ESS chip on the Buffalo on the other hand can do any sample rate from 32khz to 192khz. I use it for 192khz material every day.
Switch 3 should indeed be low. I would have to see your setup to know if something is wrong.
Cheers!
Russ
Russ White said:
Russ
No confusion; I don't have the usb board.
Setup:
spdif input to Buffalo which spdif switch on, all switches high as in as in maual Rev 0.2.
Output via Ivy.
Works only on 44.1k and 48k inputs. Lock light does not come on with 88.2k or 176.4k inputs. Have not tried 96k yet.
Also, if reset is enabled, then a reboot is needed to re-enable lock!
What's wrong???
Fred
FMAK,
Honestly, I have no way of knowing what is wrong without having my eyes/hands on your gear, but my first suspicion is the SPDIF signal itself. 🙂 Perhaps try a different source? Are you using coax? If so is it properly terminated?
For normal operation with the stock firmware:
Reset should be left open.
Address should be left open.
Cheers!
Russ
Honestly, I have no way of knowing what is wrong without having my eyes/hands on your gear, but my first suspicion is the SPDIF signal itself. 🙂 Perhaps try a different source? Are you using coax? If so is it properly terminated?
For normal operation with the stock firmware:
Reset should be left open.
Address should be left open.
Cheers!
Russ
FMAK, you may also need to set switch 4 low. (remember after setting switches you must cycle power).
Your SPDIF signal may need a wider DPLL window.
Your SPDIF signal may need a wider DPLL window.
Russ White said:
Russ
My spdif output locks on any narrow pll (<100 ppm). Supplied by PC to Apogee Big Ben and measuires accurately.
I just did what you suggested. Still won't lock on >48k.
My signak is fine. It locks on a 100 ppm dual pll dejitter box, on a rme dac, on a dCS Purcell, but not on the Buffalo with SW4 set low or high.
Actually regardless of the SW4 setting, the lock light flickers on sometimes and produces a series of pops.
I think either the comparator or the Buffalo is at fault.
Can you ship a tested one and I shall return mine.
Problem not withstanding, the Buffalo sounds v good at 44.1k but better with slow roll off.
Fred
FMAK,
Sure, send it in, but I am just surprised it would lock at all if there was a problem with the ESS chip or the comparator.
What level is the SPDIF? Is it .5V?
Someone on the forum needed to reverse the phase (swap input wires) of their transformer coupled SPDIF input.
Cheers!
Russ
Sure, send it in, but I am just surprised it would lock at all if there was a problem with the ESS chip or the comparator.
What level is the SPDIF? Is it .5V?
Someone on the forum needed to reverse the phase (swap input wires) of their transformer coupled SPDIF input.
Cheers!
Russ
Russ White said:
Russ
0.5V and looks good square wave. BNC input sockets. i will double check phase.
Where do I send it to and do you have a tested one on >48k I can have please?
Fred
ps: It just occured to me that it may also be the onboard XO. What freq is it and should I check.
Russ White said:
Weird, I reversed the spdif socket connection and itlockes at 88.2k but not 96k. Whole thing does not sound good at all!!!
What's happening?
Fred
Fred, you might check the output of the comparator with your scope.
You can get the comparator output signal at the SPDIF switch.
You can get the comparator output signal at the SPDIF switch.
Russ White said:
You mean across the switch?
What should it look like?
Re XO; does freq tolerance matter to the Sabre ?
Fred
fmak said:
With the SPDIF switch closed, measure the comparator output from either end of the switch and GND. It should look the same as the SPDIF input but level shifted upward. terminal "D2" would also be the same net, so you can use that as your measurment point too.
XO Freq just needs to be stable and clean. Exact freq is not critical. But in our case it needs to be ~80mhz to do up to 192khz SPDIF input.
Russ White said:
Russ
The comparator seems screwed up; I have very nice eye pattern on the spdif connector. At the comparator, I no longer have a crossover intersection mid way between max and min. The two square sections are now separated by a step to the negative side of the wave. Something is wrong.
Please give address to send board back to. Can you send a working one simultaneously; I am anxious to have it working at hirez!.
On limited hearing, the Ivy seems superb - very transparent which is rare.
Fred