according to ESS datasheet it shouldn't work without external 1.2V supplied to DVDD - if I'm reading the datasheet correctly, now
Agreed
Existing linear voltage regs are from Microne - can't find datasheet for them so probably need changing. Not so sure about all your individualised supplies - AVCC is hte most sensitive, I believe
Maybe overkill? Will see
Yea, output stage needs attending to
Audio clocks are NDK, I believe - conversion to synch mode is just a matter of supplying a clock synched with I2S data i.e. intending to reclock I2S lines between XMOS chip & ESS DAC
Probably but who knows best settings for SQ?
I still think if nothing else this is a decent learning platform for getting feet wet with ESS DAC chips?
NDk maybe, but probably not NDK SDA. Just that there is no or little benefit to having the best clocks if using an asynchronous dac with ASRC, especially for a rather low cost one. Doubt they buy the more expensive clocks for this dac.
The whole synchronous Sabre thing is definitely more complicated than one might imagine. Register programming required for sure, and still not easy to get the whole way there in some cases.
Some fair experience here, but some of the details are not for public discussion. What is already public is that reducing DPLL bandwidth and utilizing harmonic distortion compensation registers both can help. The potential is quite large, but hardware needs to be good enough to get the best out of it.
It will never end up as well as an ES9038Q2M board can, no matter how much effort you put into it. If that's okay, then by all means have at it.
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NDk maybe, but probably not NDK SDA. Just that there is no or little benefit to having the best clocks if using an asynchronous dac with ASRC, especially for a rather low cost one. Doubt they buy the more expensive clocks for this dac. - I agree
The whole synchronous Sabre thing is definitely more complicated than one might imagine. Register programming required for sure, and still not easy to get the whole way there in some cases. - I don't believe that is correct - from my memory of Dustin's post here, just supplying a clock that is synchronous with the I2S signal will turn off the internal ASRC - no register changes needed
Some fair experience here, but some of the details are not for public discussion. What is already public is that reducing DPLL bandwidth and utilizing harmonic distortion compensation registers both can help. The potential is quite large, but hardware needs to be good enough to get the best out of it. -Ah, well if not for public discussion, I'll just have to plough my own furrow
It will never end up as well as an ES9038Q2M board can, no matter how much effort you put into it. If that's okay, then by all means have at it.- Maybe, particularly if particular ways of getting best SQ from 9038 are proprietary/kept secret
As I said, it's probably a good platform for dipping toe in ESS pond & may result in a DAC close enough in sound to the more complicated ESS chips that it's good enough for most & makes little difference to them - I guess it's a personal balance between time, effort & money
What is allowed in public discussion is set by the ESS NDA and by forum rules about not posting confidential information. If you have an executed NDA on file with ESS then we can talk privately, that would be my understanding of how ESS has set up the legal requirements.
I can say that to 'just turn off ASRC' requires setting the DPLL register to the correct value, at least that's the case for other similar dacs.
I can say that to 'just turn off ASRC' requires setting the DPLL register to the correct value, at least that's the case for other similar dacs.
Right I found Dustin Forman's post on this - he being one of the main designers of the ESS DAC chip - see his post here and the follow on posts
dusfor99 said:
So you can see that the ASRC is effectively turned off by using a synchronous I2S clock - no register settings involved. Note "ASRC doesn't do any corrections" means the ASRC is not operating - this can be heard in practise where a low jitter source sounds better when ASRC is off (synchronous clock is supplied to ESS chip) than when using ASRC - try it yourself - don't set registers to turn off ASRC but instead supply a synch clock
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No, its not off, its 'useless.' In fact its worse than useless because only perfect clock signals will make DPLL_num perfectly stable, and sound quality will suffer anyway because DPLL VCO is still introducing its own jitter into the mix. Sounds better with it turned off. You can believe it or not. Doesn' matter. But, if you sign an NDA with ESS they will tell you I am right. You don't even have to do that. Some controller software is available that lets people turn ASRC off all the way and adjust DPLL_bandwidth as they please. DimDim's open source controller project can to it. TP Buffalo configuration allows it. Iancanada controller can do it. Lots of people have experimented with settings to see what sounds best. Its a well known fact by now if you read about what people have found.
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Ok, I don't know how you can interpret Dustin's words other than ASRC is off when IS2 clock is the same clock as fed to ESS DAC (i.e synchronous clocking)?
"Perfect clock signals" means that the ALL I2S signals are in phase with exactly the same clock as used for ESS clock - it is "relatively perfect"as there is no jitter or phase difference between BCL, LRCK Data , i2S signals & MCLK as they all derive from the same clock - assuming these I2S signals are reclocked by this clock just before it enters the ESS DAC - which is what I proposed at the very beginning of this. The DPLL cannot introduce jitter when it is not actually doing anything to the signals - there can be no DPLL activity & therefore no added jitter when there is nothing to correct. I believe that is how ESS operates internally?
What you are saying was already asked & answered in 2008 by Russ White here
You may be right but I would expect Dustin would have qualified his statements with these provisos if that were truly the case as he is an engineer & representing ESS on that thread.dusfor99 said:
has anybody tried (have you tried this?)
- synchronous clock with DPLL register setting turned off Vs
- synchronous clock with DPLL register set to highest ?
My contention (& Dustin seems to confirm it) that they are equivalent & will result in the same SQ.
Any links to such results/tests?
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Anyway, this all started from my suggested mod of routing the selected clock output signal form the two audio clocks on the Topping D10 board to replace the 100MHz clock signal that is currently input to the ESS DAC chip. I suggested that no register setting was needed for setting the ESS DAC into this sync clock mode operation.
I will do this mod when I get a chance & report
I will do this mod when I get a chance & report
Okay, on the mod, I assume the USB chip clocks are 49/45Mhz? You can use them, but you need the frequency of those clocks to be at least three times the bit-clock or DSD-clock frequency for any music you want to play. It is possible to get down to twice the frequency if DPLL = 0 and lock still occurs.
It means there will be a limit on maximum sample rates that can be played, no big deal for an experiment like that.
It means there will be a limit on maximum sample rates that can be played, no big deal for an experiment like that.
OK, I should mind my own business
But wouldn't it be better to use an opamp with less noise density?
Nope 22.xxx/24.xxxMHz
Yea, for synch clock max samplerate for 22.xxx/24.xxxMHz clocks is 176/192KHz - not really a problem
Can always use 45/49MHz clocks at a later stage if the mods proved worthwhile?
Consider the probability that things might have moved on ever so slightly since them.
Sure it's possible - I'm open to that - got any evidence that this no longer applies?
I have not signed NDA nor have been privy to any recent discussion on this, however, if it has behavior like a traditional analog PLL, there can be 'hunting' in what is referred to as the 'dead zone'. So even though the two are effectively synchronous, there is still a (D)PLL that is moving around ever so slightly. Just a guess.
Regardless, I'd say if you want to be sure, program the registers and do the job properly, disable the DPLL.
T
Mark, just to get an overall update, your original target was to get close or equal to the DAC3.
Do you feel you have achieved this? Are we looking at a scenario of moving past the DAC3 with the latest mods? If this is the case, do you have any other 'benchmarks' (pun intended) to compare.
I still have to say I'm not convinced WRT AK4499. The eval data sheet shows some worrying information, namely all those distortion curves on P28 with various VREF capacitor setups.
In chasing ultimate DR and hence the massive current swings and low OP impedance that goes with it, it looks like they have created a hyper sports car like DAC that is very difficult to optimize, subjectively and objectively.
I really wish T.I. had further developed their current segment DACs. IMO, that process had the potential to match or surpass all of these resistor array DACs. Maybe they lost some design talent?
T
I am not so worried about that.
It is the same on the AK4490. I think this is due to the VREF supply and filtering.
For some reason AKM still use the same VREF regulator as used on the AK4490 EVB. It is rather noisy. To reduce the noise, RC filters are used on the VREF. But this increases the effective output impedance of the regulator. To counter that, huge capacitors are used to reduce the impedance seen by the VREF inputs.
On the RTX6001 I used the LT3042 as VREF supply for the AK4490, with no additional filters. So the impedance seen by the VREF inputs is the output impedance of the LT3042. The LT3042 has very low noise, so it doesn't need the additional filter, which would ruin the impedance at low frequencies.
With the AK4490 in the RTX6001 I did not see the increased distortion at low frequencies. I assume that the same will be possible with the AK4499. I hope to test it at some point, but right now I don't have the AK4499 available.
4490 is a completely different architecture so not much point in making comparisons.
I think with the parallel resistor OP architecture, the 4499 will have very
different characteristics to the voltage OP switched cap 4490. There are massive current swings in the 4499. Also note the separate I-V opamp feedback return pins which is most likely a separate current path back to the internal summing point of the resistors.
WRT VREF noise, something to think about:
Noise on VREF should be common mode to each + and - DAC OP phase. The evaluation board does not have a 'summing' or, dif to SE converter stage, however, that doesn't matter as AP test set is a balanced input and has very high common mode rejection, especially at low frequencies. So a lot of that noise should be rejected, how much is the question.