Enhancement mode JFET

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#21
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#29
scott wurcer said:
The OP showed standard Shockley model JFET's.
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Yes, and there's no issue running a n JFET with slightly positive gate bias, before the GS source becomes forward biased and loses control over the channel. The idea is to use a super thin (0.5um here) channel and lightly doped, just enough so that the drain space charge region touches the source, and therefore the JFET is off at Vgs=0. Biasing the gate slightly positive is just enough to "un-pinch" the channel and allow the current to flow between source and drain.

The big issue with such a silicon normal off JFET is if a max 0.3-0.4V of positive gate bias is enough to provide the required transconductance. Such a device would inherently have a very limited transconductance, therefore it would require a huge silicon area to compensate. The patent actually describes a dual channel device, in which there is a floating drain, increasing the transconductance per unit area. This is probably the only added value in this patent, but as for a practical implementation it appears to me both complex and critical in process.

If I remember correctly, years ago JC claimed he used his beloved 2SK/2SJ JFETs with a slightly forward gate bias, to get the last drop of transconductance. Same idea here, for a device with zero pinch voltage.
 
#31
The first XEON chipset used tiled layers on die with a much narrower process to fuse them together at points.

I don't know if there's a pill for that.

Time to start thinking about a transistor as a micro device.

Wait, isn't there a company that does that already?!?
 
#35
syn08 said:
If I remember correctly, years ago JC claimed he used his beloved 2SK/2SJ JFETs with a slightly forward gate bias, to get the last drop of transconductance. Same idea here, for a device with zero pinch voltage.
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Yes, I understand the argument and you are correct. Considering the Vp range of a standard process there would be no practical way to guarantee Vp not going negative or, in other words, the enhancement vs depletion mode of operation becomes a gray area. I could see some single supply circuits where no negative supply is ever needed but Vp guaranteed >= 0 is not practically achievable. OTOH my last circuit had a JFET op-amp at the input that ran on the end of life voltage of a coin cell with the JFET's deeply into the triode region with no ill effects.

EDIT - You also need to go back to first principles since the Shockley equations for the JFET fail at Vp = 0.
 
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#36
Correct, otherwise said, for forward biased junctions (Vgs>0) the space charge region does no longer follows the well known square law with the drain voltage (for abrupt junctions). And even otherwise said, the charge neutrality is no longer valid, one has to consider the effect of the current flows, which as far as I am aware of (I'm becoming rusty, though) has no closed form solution. Simulations starting from the Boltzmann transport equation is the only way to accurately model what happens in this shady area of slightly forward biased gate, and to add insult to injury, the problem is at least 2D. Been there, done that, for other weird 2/3D devices, it's not for the faint of heart.
 
#37
Been there, done that, for other weird 2/3D devices, it's not for the faint of heart.
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BTW all the capsule microphones operate this way, biased at Ig = the drain to gate leakage. There is one FET geometry that fails to work, I forgot the number but it was the classic Siliconix electrometer FET. With drain positive and the gate floating there was 0 drain current so the FET acted like it was pinched off with no gate potential. No one in the fab could ever explain it.
 
#39
ALD does manufacture what they call 'zero threshold (tm)' MOSFETs. To all intends and purposes that is an 'in between' MOSFET.
Neither enhancement nor depletion. Or both ;-)

See for instance the ALD210800A. Not discrete, but still.

As they say:

Gate Threshold Voltage VGS(th) values range from -3.50V Depletion Mode to +3.50V Enhancement Mode devices, including
standard products with VGS(th) specified at -3.50V, -1.30V, -0.40V, +0.00V, +0.20V, +0.40V, +0.80V, +1.40V, and +3.30V. ALD can
also provide any customer-desired VGS(th) between -3.50V and +3.50V on a special order basis.

Jan
 
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#40
syn08 said:
As I said, these are crazy complex and cannot be, by any means, implemented in a pure bipolar process (this is for BICMOS), or even less for discrete devices.
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Maybe I spoke too soon originally but taking into account the forward bias issues on the gate of a JFET a useful device with a guaranteed positive Vt over the full temperature range is not practical even though you can technically use a JFET with slight forward bias.
 
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