Hello BenMah,
already done. Q1 and Q2 are doubled up. For Q1 you can use for example 2 J113 or 2 SMD-JFets (2SK209, 2SK3557,...). Same for Q2.
If you double and match the J113s at Q1/Q2 (4 JFets) you can lower the distortion also.... Many possibilities for experiments.
Cheers
Dirk
already done. Q1 and Q2 are doubled up. For Q1 you can use for example 2 J113 or 2 SMD-JFets (2SK209, 2SK3557,...). Same for Q2.
If you double and match the J113s at Q1/Q2 (4 JFets) you can lower the distortion also.... Many possibilities for experiments.
Cheers
Dirk
How can we attach this heatsink to a SMD-JFet
https://www.aliexpress.us/item/2251...tewayAdapt=glo2usa4itemAdapt&_randl_shipto=US
https://www.aliexpress.us/item/2251...tewayAdapt=glo2usa4itemAdapt&_randl_shipto=US
with this ?2SK209 will be OK for the diff pair. And they will perform better there.
They won't stand the dissipation in the current source.
But J113 is OK for those positions.
We have a custom adaptor board which turns SOT23-3 into TO92.
Size is 5x5mm.
Costs extra even if you can find a shop willing to make them.
View attachment 1131356
Patrick
Hello out there,
I did some homework: matching / measuring a lot of J113s. Although I had a lot of J113 measured before (data written down), It was a little pain
to get an octett out (Q1 and Q2 doubled up = 4 and the same for the other channnel = 8. And another quartett for the CCS (Q3/Q4). I have such
a damage
Perhaps I need a therapy?
Waiting for some parts to be delivered...
Cheers
Dirk
I did some homework: matching / measuring a lot of J113s. Although I had a lot of J113 measured before (data written down), It was a little pain
to get an octett out (Q1 and Q2 doubled up = 4 and the same for the other channnel = 8. And another quartett for the CCS (Q3/Q4). I have such
a damage

Waiting for some parts to be delivered...
Cheers
Dirk
Attachments
Hello mbrennwa,
I checked the 2SK240BL-datasheet. Gate pins are in the mid (D-G-S)
(D-G-S).
Doubled J113 have gate -pin on outside. (G-S-D)
(G-S-D)
So would only be possible with twisted legs.
Cheers
Dirk
I checked the 2SK240BL-datasheet. Gate pins are in the mid (D-G-S)
(D-G-S).
Doubled J113 have gate -pin on outside. (G-S-D)
(G-S-D)
So would only be possible with twisted legs.
Cheers
Dirk
Since you're comparing to doubled J113, are you considering paralleled parts? While it would certainly be an interesting idea to use paralleled 2SK170 (i.e., 4x 2SK170 or 2x 2SK240 per channel), I was not thinking of paralleled parts. My idea was to use one 2SK240BL part for the differential input.Hello mbrennwa,
I checked the 2SK240BL-datasheet. Gate pins are in the mid (D-G-S)
(D-G-S).
Doubled J113 have gate -pin on outside. (G-S-D)
(G-S-D)
So would only be possible with twisted legs.
No matter what, I guess I'll have to start matching my 2SK240BL parts...
I made a test PCB, too. But I could get the offset below 2VDC.
The Iq of first stage is about 3mA, the second stage CCS is about 9mA,
The first stage Jfets are matched to 0.01mA at Id 1.5mA and Vds 25.5V .
The VAS transistor tested are 2SA1382 and ZTX735 while waiting for KSA992.
The Iq of first stage is about 3mA, the second stage CCS is about 9mA,
The first stage Jfets are matched to 0.01mA at Id 1.5mA and Vds 25.5V .
The VAS transistor tested are 2SA1382 and ZTX735 while waiting for KSA992.
Attachments
Made some progress today.
as Pa is used to say ... you'll see some crosstalk

Patrick, OT to this circuit, but how do you put .op labels on an LTSpice schematic that show current? I've given up from searching. Thanks.And a Spice file for Nelson's circuit to play with.
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