Is anyone still working on this? I like the idea of rolling your own R/2R dac, but it seems an IC is really the best way to get accuracy for the resitors, with laser trimming, and small size to keep an even thermal environment - plus RF issues in the layout?
I can't help think there must be a way to have calibrating feedback of some kind, instead of relying on perfect resistors, etc, but I'm sure someone much cleverer than I would have thought of it, if so.
I can't help think there must be a way to have calibrating feedback of some kind, instead of relying on perfect resistors, etc, but I'm sure someone much cleverer than I would have thought of it, if so.
Thinking
And what am I thinking about?
I found out that the CXD1225 chip used in e.g. Sony players has a sixteen channel parallel discrete output.!
- special note: it can be forced into double upsampling WITHOUT a digital filter in place. Cool. 😎
Also a CXD1088 oversampling digital filter exists that has the same discrete output.
This would be easy to incorporate in a DAC, stand alone.
So I have that as a candidate for a project, and yes it would be nice to discuss that.
Eventually, I would like someone to design a circuitboard, to make things more tidy.
albert
And what am I thinking about?
I found out that the CXD1225 chip used in e.g. Sony players has a sixteen channel parallel discrete output.!
- special note: it can be forced into double upsampling WITHOUT a digital filter in place. Cool. 😎
Also a CXD1088 oversampling digital filter exists that has the same discrete output.
This would be easy to incorporate in a DAC, stand alone.
So I have that as a candidate for a project, and yes it would be nice to discuss that.
Eventually, I would like someone to design a circuitboard, to make things more tidy.
albert
Yes I am all exioted.
It has a special mode to set it in this parallel output.
The CXD1088 stows the parallel output
- pin 33 = MSB
- Pin 34 to 38 = D2 to D6
- pin 39to 44 = D7 to D11
- pin 1-5 = D 12-16
A similar output arrangement exists in the CXD1225.
But Bernard, tell me, how do you get the R2R parallel output? Through a bit counter?
albert
CXD1088AQ datasheet pdf datenblatt - Sony Corporation - Over Sampling Digital Filter LSI ::: ALLDATASHEET :::
As far as measurements go, I could settle at 12 +1 sign bit / 192ksps, and that would be cool because of the non segmented ladders. Some feedforward error correction would be necessary though .
If you want 20 real world bits without averaging , then I guess Im not the person to ask . 😀
If you want 20 real world bits without averaging , then I guess Im not the person to ask . 😀
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Hi,
Fancy meeting you here. Funny someone resurrected this thread. Fun to read what my evil twin wrote six years ago.
Well, how about I propose the following:
1) Fast FPGA with enough capacity to do "interesting" (sinc compensation instead of zero stuffing) digital filters of 4 - 8 * OS for single speed application (one may call this synchronous re-sampling to 352.8KHz or 384KHz) with the option to omit the re-sample always to the same (8 Speed) factor with 8 Speed sample rate signals being left original entierly.
2) Use FPGA resources to implement a FIFO memory buffer and logic to control an external 12bit DAC that controls two VCXO (90.3168MHz and 98.304MHz with 300PPM pull range) to allow the DAC to be reasonably impervious to source jitter etc. as long as the source's average sample rate output is within around +/-150 ppm of nominal.
It may be possible to incorporate an SPDIF receiver as well, as we are here already with optional I2S input.
3) Use a 256 Level PWM modulator (256 * Fs) on the voltage being send into a R2R DAC, to give effectively a 8-Bit "Delta Sigma" DAC without noiseshaping for the 8 MSB's.
4) Use a 16 Bit R2R DAC after the modulator (this can be attained with some care using commercial grade resistors etc.) to provide the 16 LSB's. Use resistor of sufficiently low value to keep noise low.
So the R2R DAC operates at around 400KHz with it's reference voltage modulated (and lowpassed) for the higher bits.
It may not provide true 24 Bit linearity or DNR, but it should be possible to come close and the results should at least be interresting in their own right and provide an alternative to say an ESS Hyperstream DAC, so to speak an "old school" alternative.
Anyone good enough with FPGA's to make the VHDL for this? Then I may be able to attend to the rest.
Ciao T
Fancy meeting you here. Funny someone resurrected this thread. Fun to read what my evil twin wrote six years ago.
Well, how about I propose the following:
1) Fast FPGA with enough capacity to do "interesting" (sinc compensation instead of zero stuffing) digital filters of 4 - 8 * OS for single speed application (one may call this synchronous re-sampling to 352.8KHz or 384KHz) with the option to omit the re-sample always to the same (8 Speed) factor with 8 Speed sample rate signals being left original entierly.
2) Use FPGA resources to implement a FIFO memory buffer and logic to control an external 12bit DAC that controls two VCXO (90.3168MHz and 98.304MHz with 300PPM pull range) to allow the DAC to be reasonably impervious to source jitter etc. as long as the source's average sample rate output is within around +/-150 ppm of nominal.
It may be possible to incorporate an SPDIF receiver as well, as we are here already with optional I2S input.
3) Use a 256 Level PWM modulator (256 * Fs) on the voltage being send into a R2R DAC, to give effectively a 8-Bit "Delta Sigma" DAC without noiseshaping for the 8 MSB's.
4) Use a 16 Bit R2R DAC after the modulator (this can be attained with some care using commercial grade resistors etc.) to provide the 16 LSB's. Use resistor of sufficiently low value to keep noise low.
So the R2R DAC operates at around 400KHz with it's reference voltage modulated (and lowpassed) for the higher bits.
It may not provide true 24 Bit linearity or DNR, but it should be possible to come close and the results should at least be interresting in their own right and provide an alternative to say an ESS Hyperstream DAC, so to speak an "old school" alternative.
Anyone good enough with FPGA's to make the VHDL for this? Then I may be able to attend to the rest.
Ciao T
Tritosine,
The CXD1088 running at 4x OS :
- pin 31 to H = select parallel mode
- pin 23 indicates word length: H = 18 bits, L = 16 bits if SONY output is chosen.
- pin 32 = LRCK output with 4fs
- pin 24 specifies format: H = I2S and L = SONY format
This, with just using the top bits would make you happy I guess. A DF is embedded in the chip though .
Though I would prefer 12 or 14 bits sampled individually * 192ks/sec -> this arrangement here given only will give copied interpolated samples, not hifi I guess.
Using this DF chip would make life easier than using discrete logic, I think.
albert
Hi Dave,
I saw this indeed but it looked complex to me. All those wires, a nightmare in soldering.
The ready printplates R2R plates (SMD 50k/25k ladder) does look interesting though. I would expect quite some capacitance leakage.
albert
-the MSBtech discrete ladders look remarkably simple. Too bad we dont know how good are these as far as differential nonlinearity goes. But hey, this is like asking SNR of a straight 1bit design .
Linear Technology - LTC2757 - 18-Bit SoftSpan IOUT DAC with Parallel I/O
-looks like decent spec and a decent price to match.
I have a several of the old 16bit DIP parallel parts if someone wants a few.
-looks like decent spec and a decent price to match.
I have a several of the old 16bit DIP parallel parts if someone wants a few.
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what exactly are you suggesting ?
there's nothing new about this chip other than being 18 bit.
there are already a few 16 bit monolithic, current output, serial and parallel input chips from TI (DAC8811/2/4 and DAC8820/2).
and you consider $85 a pop a decent price ??
there's nothing new about this chip other than being 18 bit.
there are already a few 16 bit monolithic, current output, serial and parallel input chips from TI (DAC8811/2/4 and DAC8820/2).
and you consider $85 a pop a decent price ??
Then perhaps compare those DNL plots more closely . Also those 1-4 plots inside the 8814 !
No question it wipes the floor with th TI parts.
BTW , all grades are guaranteed 18bit monotonic so it goes for 30+x . Once you parallel a few and apply some trick 20+bit is well within reach.
No question it wipes the floor with th TI parts.
BTW , all grades are guaranteed 18bit monotonic so it goes for 30+x . Once you parallel a few and apply some trick 20+bit is well within reach.
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