Well, since control theory has been mentioned, I shall suggest a nice "control" idea to handle the instability issue. From first principles, instability is the same as the capacitor voltage running on its own instead of obeying the audio signal. However, it is not possible for the capacitor to misbehave without the inductor knowing about it, since inductor current is what charges / discharges the capacitor. The method, called current-mode control, uses two cascaded loops, with the outer (slower) loop for voltage control. Going digitally, you'd need two ADCs or a two-channel ADC.
From the circuit below, it is easy to see how a large positive capacitor voltage error (Vout > Vref) cancels itself by driving an inductor current of the opposite polarity. This is probably the simplest way to get PFFB and it works because the inductor current is simply the sum of the currents through the speaker and the capacitor (by Kirchoff's law).
If you want performance, then trying to compensate the phase (locally) would not help much. It maybe possible to "push" the oscillation frequency an octave or so, that's it. Remember that delay is time and it is not possible to unwind / reverse time or cancel the phase delay to get excellent stability without losing performance.
The devil is in the control theory, as has been mentioned. Look up Bruno Putzeys, the designer of the UCD, Ncore, and Purifi class d amps. He was able to solve the math required to predict the behavior of the control loop.
I'm probably being awfully naive, but I wonder if you get away with something like this when you want to make a conditionally-stable high-order feedback loop. It's essentially a fifth-order sigma-delta modulator with embedded pulse width modulator with feedback from the analogue side. The extra digital feedback to the third integrator is there because otherwise I was one zero short to make it stable. The first two integrators definitely need state variable limiting or a reset for recovery from clipping, I'm not at all sure if that suffices. The digital positive feedback at the top corrects for the fact that the ADC digitizes the difference between the output signal and the output of the analogue second-order filter at the bottom, rather than just the output signal. Multiplications by coefficients and decimation and interpolation stages left out for clarity.
Edit: I got the sign of the digital feedback at the top wrong, it should be negative.
Edit: I got the sign of the digital feedback at the top wrong, it should be negative.
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Interestingly, the concept of deliberately inducing self-oscillation in a Class-D amplifier to maintain a steady state at startup. However, this approach necessitates exploring new areas of study, such as dynamic control theory, to address various conditions and recovery issues, including integrator windup and behavior near clipping, where the switching frequency drops to half the rate and other matters like keeping fsw stable.
In this context, we move beyond the realms of Digital Signal Processing (DSP) and Field-Programmable Gate Array (FPGA) techniques. Instead, we delve into more traditional control theory concepts, involving pole/zero analysis, computation, and Proportional-Integral-Derivative (PID) methods.
By the way the supplied compensation network is meant to prevent oscillation in buck converters power supplies isn't it.
In this context, we move beyond the realms of Digital Signal Processing (DSP) and Field-Programmable Gate Array (FPGA) techniques. Instead, we delve into more traditional control theory concepts, involving pole/zero analysis, computation, and Proportional-Integral-Derivative (PID) methods.
By the way the supplied compensation network is meant to prevent oscillation in buck converters power supplies isn't it.
I think a problem of the system of post #24, besides the wrong polarity of the digital feedback, is the fact that various paths have to match. When the two paths that are subtracted to produce the ADC input signal don't match well enough in gain and phase, the ADC input signal is reduced less than anticipated, so the required ADC dynamic range gets more important. When the positive feedback via the 2nd order analogue filter at the bottom and via the ADC isn't equal but opposite to the digital feedback at the top (which should be negative but was drawn wrong), you effectively have a (positive or negative) local feedback loop across the three integrators that spoils the loop gain of the overall loop.
I agree with that Bruno Putzeys' self-oscillation idea is a unique solution to the loop gain / stability tradeoff. However, it maybe difficult to pursue such ideas in the digital domain due to the high rates required to sample at switching frequency. The math is simple as you're into oscillation as opposed to not oscillating which is the OP's case.
Multiple feedback does reduce the phase turned but doesn't use 100% of the capacitor voltage for control, instead a combination of pre and post filter feedback schemes.
EDIT: I still do not understand why the OP is not attempting to do a simple hysteretic Class-D. The control law is simple : If the output voltage exceeds/falls below the expected value by a small amount (hysteresis band), then switch the MOSFETs the other way, that's it.
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I think anything with a varying frequency would be a disaster in a digital design unless the ADC sample rate can be phase-locked to it to keep aliasing products out of the audio band.
Thank you for all the replies! I've seen them in a timely matter but wanted to do more research before replying.
I have a couple of ideas besides the ones already suggested for circumnavigating the requirement for a lower-latency ADC in a cost-effective manner.
1. Use the onboard continuous comparator to create a simple continuous time Delta-Sigma ADC that runs at the PWM modulator's clock speed. One thing I'm unsure of is whether I could simply use a binary FIR filter and add the error after the PWM generation or whether the output has to be decimated and added before DS modulation.
2. Use BD modulation like the paper suggests, and suppress the resultant EMI through CM modulation or a first order, high corner frequency output filter. This should give me more phase margin to work with than the full LC filter.
3. Bite the bullet and use an external, high-speed ADC. The reason I'd rather not do this is that high speed ADCs render the cost-saving aspect of digitizing the amplifier almost moot when there are 8 channel DACs for 35$.
Wouldn't I still need lower latency ADCs for ACMC? If for nothing else than the inner current control loop? If not, this might be worth a try, since the Certus-NX has two ADCs anyways.
Just to clarify, is this because/related to the fact that you cannot have negative group delay without attenuation?
I've looked through his papers previously, and implemented (admittedly in a non-performant way) the mathematical model he suggests in his 2009 paper. I lack the knowledge to linearly approximate the discrete time elements in a digital feedback loop, but I hope I'll be able to model such a system in the nearish future.
Wouldn't integration of the error signal not affect overall frequency response?
Only under clipping/extreme conditions should the error voltage rise over a small level. The nice thing about digital is that clipping detection and subsequent compensation is fairly simple. As for gain matching the error of the PWM synthesizer and the power stage error, I believe its not critical since the error sources are somewhat independent? Something to look into further, but the paper I linked in the original post doesn't dwell on it.
I also believe that hysteresis control would be suboptimal for a digital implementation. The triangle wave's slope at the comparators input is limited by bit depth and clock speed, so wouldn't one of those have to be variable?
I have a couple of ideas besides the ones already suggested for circumnavigating the requirement for a lower-latency ADC in a cost-effective manner.
1. Use the onboard continuous comparator to create a simple continuous time Delta-Sigma ADC that runs at the PWM modulator's clock speed. One thing I'm unsure of is whether I could simply use a binary FIR filter and add the error after the PWM generation or whether the output has to be decimated and added before DS modulation.
2. Use BD modulation like the paper suggests, and suppress the resultant EMI through CM modulation or a first order, high corner frequency output filter. This should give me more phase margin to work with than the full LC filter.
3. Bite the bullet and use an external, high-speed ADC. The reason I'd rather not do this is that high speed ADCs render the cost-saving aspect of digitizing the amplifier almost moot when there are 8 channel DACs for 35$.
The variation in frequency about the centre has been shown to be f = fo (1-m^2), where m is the modulation index. Since the implementation is digital (and high bit-depth), it becomes possible to vary the hysteresis band along the same lines i.e. B = Bo (1-m^2), to get a constant switching frequency similar to PWM.
- https://backend.orbit.dtu.dk/ws/portalfiles/portal/3973726/Poulsen.pdf
- Chapter 7 of https://www.academia.edu/1182944/Minimizing_distortion_in_self-oscillating_switching_amplifiers
Since 1-bit is where analogue meets digital, it naturally becomes a bridge between A / D worlds ....
The PWM frequency of BD is simply double that of AD, so you get an octave that's it.
You could have temporarily negative group delay (e.g. high shelf filter) but anything that has monotonically increasing phase violates causality.
Yes, at least ten times as fast as that of the outer loop.
Multiple Interleaved ADCs ...
@telluric I think my remark about the first-order slope was indeed wrong, but I'm still not sure this will work. To the extent that you can model the output stage as a buffer that adds an error E and assuming both filters and both path gains match, the output of the integrator will just be E low-pass filtered and integrated to time, no matter what the loop does.
You could go beyond BD (3-level) modulation to multi-level PWM and increase the effective switching frequency to allow a filter with higher cutoff that also has a delay small enough to be compensated with decent stability margins.
Here's a paper on how it could be done. It should be straightforward to implement in the digital domain.