Hi everyone,
I've recently started messing around with FPGAs, and, though this is possibly very naive, wanted to try my hand at digital class D. I found an IEEE paper titled A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop that I wanted to implement on an FPGA. However, the paper prioritizes power efficiency over fidelity, and (from what I can tell) neglects post-filter feedback. I've attached a block diagram illustrating essentially what the paper describes, but with post instead of pre-filter feedback. Though it still requires a high sampling rate for stability, the paper's approach relaxes the distortion requirements on the ADC, to a point where it seems hi-fi digital class D might be accessible to us DIYers, instead of being firmly locked behind expensive, proprietary chips like Axign's. I have little formal background in EE or control theory (I'm currently a Comp Sci student), so please call out any basic mistakes I've made or fundamental misconceptions I have. I would appreciate any feedback on the theory and, if its sound, further development of this project as the thread progresses.
I've recently started messing around with FPGAs, and, though this is possibly very naive, wanted to try my hand at digital class D. I found an IEEE paper titled A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop that I wanted to implement on an FPGA. However, the paper prioritizes power efficiency over fidelity, and (from what I can tell) neglects post-filter feedback. I've attached a block diagram illustrating essentially what the paper describes, but with post instead of pre-filter feedback. Though it still requires a high sampling rate for stability, the paper's approach relaxes the distortion requirements on the ADC, to a point where it seems hi-fi digital class D might be accessible to us DIYers, instead of being firmly locked behind expensive, proprietary chips like Axign's. I have little formal background in EE or control theory (I'm currently a Comp Sci student), so please call out any basic mistakes I've made or fundamental misconceptions I have. I would appreciate any feedback on the theory and, if its sound, further development of this project as the thread progresses.
Attachments
I can't read the file, but just wanted to note that you will need a high performance, low-latency ADC for the feedback. Most high-performance audio ADCs are sigma-delta ADCs with a built-in digital low-pass filter that causes much too much latency. Sometimes you can access the modulator output directly, but then you have enormous amounts of out-of-band quantization noise that the loop should not respond to.
If I remember well, there are members here who use high-performance SAR ADCs in DIY audio measuring equipment. Maybe that would be an option.
If I remember well, there are members here who use high-performance SAR ADCs in DIY audio measuring equipment. Maybe that would be an option.
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By the way, I put two very basic DIY continuous-time sigma-delta modulators on this forum, but their performance is poor.
https://www.diyaudio.com/community/...h-op-amps-and-logic-gates.320888/post-5425021
https://www.diyaudio.com/community/...ecking-raw-dsd-interfaces.316898/post-5295843
https://www.diyaudio.com/community/...h-op-amps-and-logic-gates.320888/post-5425021
https://www.diyaudio.com/community/...ecking-raw-dsd-interfaces.316898/post-5295843
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Well, for interested members, the basic idea behind the paper in the first post seems to be to:
1) Obtain the error signal output outside of the digital modulator by subtracting the reference from the output.
The input stage of the CT-DSM .... consists of an integrator that senses the differential output voltage ... into a current which is integrated by the first
stage of the CT-DSM. At the same time a digitally controlled switch produces a replica of the PWM-signal ... that cancels the major part of the sensed signal. In
this way only the error between the digital PWM signal and the analog output needs to be processed in the feedback loop.
2) Assume this error to be small and thereafter use a continuous time delta-sigma modulator (CT-DSM) for feedback, thereby avoiding filtering.
In order to relax the requirements on the ADC only the error-signal is processed which is usually very small. This opens the possibility to scale the input signal
to the ADC in the analog domain, then perform the A/Dconversion and scale down the signal in the digital domain.
Meanwhile, the OP's interest is in taking the feedback from after the filter and thereafter operate in a manner similar to that mentioned in the paper.
1) Obtain the error signal output outside of the digital modulator by subtracting the reference from the output.
The input stage of the CT-DSM .... consists of an integrator that senses the differential output voltage ... into a current which is integrated by the first
stage of the CT-DSM. At the same time a digitally controlled switch produces a replica of the PWM-signal ... that cancels the major part of the sensed signal. In
this way only the error between the digital PWM signal and the analog output needs to be processed in the feedback loop.
2) Assume this error to be small and thereafter use a continuous time delta-sigma modulator (CT-DSM) for feedback, thereby avoiding filtering.
In order to relax the requirements on the ADC only the error-signal is processed which is usually very small. This opens the possibility to scale the input signal
to the ADC in the analog domain, then perform the A/Dconversion and scale down the signal in the digital domain.
Meanwhile, the OP's interest is in taking the feedback from after the filter and thereafter operate in a manner similar to that mentioned in the paper.
Attachments
Sorry about the file format, and thank you TNT for posting the PNG.
I have a couple ADCs in mind–the only thing I'm unsure of (due to my lack of control theory knowledge) is how much latency is acceptable before instability occurs. If <200ns is acceptable, I'm considering the AD7388-4 as an option. If lower latency is required, lower bit depth and higher THD flash/two-step ADCs might be acceptable. With an analogue gain of 256 (8 bits), THD should be decreased by around 50db.I can't read the file, but just wanted to note that you will need a high performance, low-latency ADC for the feedback. Most high-performance audio ADCs are sigma-delta ADCs with a built-in digital low-pass filter that causes much too much latency. Sometimes you can access the modulator output directly, but then you have enormous amounts of out-of-band quantization noise that the loop should not respond to.
If I remember well, there are members here who use high-performance SAR ADCs in DIY audio measuring equipment. Maybe that would be an option.
Very nice! I don't think anything I could implement except a flash ADC would be fast enough, or cost effective enough to make it worthwhile. Keep up the good work though.By the way, I put two very basic DIY continuous-time sigma-delta modulators on this forum, but their performance is poor.
https://www.diyaudio.com/community/...h-op-amps-and-logic-gates.320888/post-5425021
https://www.diyaudio.com/community/...ecking-raw-dsd-interfaces.316898/post-5295843
Exactly, however I'm not sure if a CT-DSM is necessary/makes a difference compared to other ADC architectures. Furthermore, I don't know if an active, unloaded, critically damped filter on the low level PWM output will serve as an adequate error reference to compensate for non-linearities in the power stage and output filter.Well, for interested members, the basic idea behind the paper in the first post seems to be to:
1) Obtain the error signal output outside of the digital modulator by subtracting the reference from the output.
The input stage of the CT-DSM .... consists of an integrator that senses the differential output voltage ... into a current which is integrated by the first
stage of the CT-DSM. At the same time a digitally controlled switch produces a replica of the PWM-signal ... that cancels the major part of the sensed signal. In
this way only the error between the digital PWM signal and the analog output needs to be processed in the feedback loop.
2) Assume this error to be small and thereafter use a continuous time delta-sigma modulator (CT-DSM) for feedback, thereby avoiding filtering.
In order to relax the requirements on the ADC only the error-signal is processed which is usually very small. This opens the possibility to scale the input signal
to the ADC in the analog domain, then perform the A/Dconversion and scale down the signal in the digital domain.
Meanwhile, the OP's interest is in taking the feedback from after the filter and thereafter operate in a manner similar to that mentioned in the paper.
The usable bandwidth should be much higher than the cutoff for the output filter and the reference LPF, wouldn't that along with the CT error integrator remove most frequencies high enough to cause aliasing problems?
I don't know. Maybe it is, as long as the ADC sample rate is an exact integer multiple of the PWM frequency.
Is it possible to use the instability that occurs (from a late ADC) to get a digital self-oscillating modulator, as in a ring oscillator etc. ? If so, a regular ADC with a constant predictable delay could be used. The switching frequency may vary but that shouldn't be a problem for recovering the audio.I have a couple ADCs in mind–the only thing I'm unsure of (due to my lack of control theory knowledge) is how much latency is acceptable before instability occurs.
I doubt if that would work when the delay is in the hundreds of microseconds, like a sigma-delta audio ADC with linear-phase decimation filter would have.
Besides, I think it would be a good idea to use an ADC sample rate that is a multiple of the PWM rate. The harmonics of any PWM ripple that enters the ADC then alias to a DC offset or to a multiple of the PWM frequency (if they alias at all) and PWM ripple on the reference doesn't cause any mixing products you didn't already have anyway.
Besides, I think it would be a good idea to use an ADC sample rate that is a multiple of the PWM rate. The harmonics of any PWM ripple that enters the ADC then alias to a DC offset or to a multiple of the PWM frequency (if they alias at all) and PWM ripple on the reference doesn't cause any mixing products you didn't already have anyway.
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Possibly? I think it would be more computationally expensive though, as feedback would have to be sampled closer to the PWM rate.Is it possible to use the instability that occurs (from a late ADC) to get a digital self-oscillating modulator, as in a ring oscillator etc. ? If so, a regular ADC with a constant predictable delay could be used. The switching frequency may vary but that shouldn't be a problem for recovering the audio.
I plan on sampling the ADC at 8x the DSM rate, or 1/32 the PWM sampling frequency. I'm actually considering using the ADCs onboard the Certus-NX to save cost, as they're 12b, have decent noise performance, and sample at 1MSPS. My logic is that, even with 1us delay in the feedback, the feedback should have a significant gain margin at 1Mhz because we're sampling after a 3rd order filter with a corner frequency around 30khz. Thus, oscillation should be suppressed. Does this sound feasible?I doubt if that would work when the delay is in the hundreds of microseconds, like a sigma-delta audio ADC with linear-phase decimation filter would have.
Besides, I think it would be a good idea to use an ADC sample rate that is a multiple of the PWM rate. The harmonics of any PWM ripple that enters the ADC then alias to a DC offset or to a multiple of the PWM frequency (if they alias at all) and PWM ripple on the reference doesn't cause any mixing products you didn't already have anyway.
It's not only about delay, it is also about the order of the loop. The baseline is that you have a second order filter in the loop that turns about 180* at high frequencies, leaving you with poor inherent phase margin. Any additional phase shift from the ADC / other parasitics would simply make this 180* happen much earlier in frequency. And there's also the issue of the loudspeaker not being a neat resistive load that makes stabilising a a post-filter feedback class-d amp very difficult if not impossible, irrespective of the domain being digital or analogue.
If it doesn't work, you could always adopt a multilevel PWM and reduce the filter delay until the required stability margins are achieved.
If it doesn't work, you could always adopt a multilevel PWM and reduce the filter delay until the required stability margins are achieved.
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Many over the years here has attempted this and the thread will die for obvious reasons. A few RC chains an OPAMP + Comparator does everything, but then again the Mathematics isn't well understood, most cannot even solve a 5-pole compensator control feedback. FPGA for Radar or High speed radio sampling. and processing.
Ah, I see. Would a digital linear phase filter after the ADC help? That way gain margin could be increased without lowering the unstable oscillation frequency.It's not only about delay, it is also about the order of the loop. The baseline is that you have a second order filter in the loop that turns about 180* at high frequencies, leaving you with poor inherent phase margin. Any additional phase shift from the ADC / other parasitics would simply make this 180* happen much earlier in frequency. And there's also the issue of the loudspeaker not being a neat resistive load that makes stabilising a a post-filter feedback class-d amp very difficult if not impossible, irrespective of the domain being digital or analogue.
If it doesn't work, you could always adopt a multilevel PWM and reduce the filter delay until the required stability margins are achieved.
I by no means claim this approach to be novel. Are you saying this is not a feasible idea without the funding and engineering department of a large company? Though the details of their implementation are unknown, Axign shows that PFFB digital class D is possible, and this paper shows a technique to reduce the ADC requirements that have been a limiting factor in HiFi digital class D.Many over the years here has attempted this and the thread will die for obvious reasons. A few RC chains an OPAMP + Comparator does everything, but then again the Mathematics isn't well understood, most cannot even solve a 5-pole compensator control feedback. FPGA for Radar or High speed radio sampling. and processing.
I think functionality could be had if compromises in performance are made for example, by lowering the loop gain. Note that no SMPSs take feedback from before the filter but they're all still stable and functional.
Any filter adds to the delay in the loop to give the same consequences. For the pre-filter feedback case, the huge 180* phase shift of the LC filter is not present and therefore better stability is inherently possible. When you pull feedback after the filter, this 180* phase margin suddenly disappears.Would a digital linear phase filter after the ADC help?
Linear-phase filters have more phase shift than minimum-phase filters (the purely theoretical ones that predict the future excepted).
In principle, you could to some extent correct for the phase shift of the LC filter with an inverse filter after the ADC. Just make a digital minimum-phase filter that has an upward second-order slope from the frequency where the LC filter response starts to drop.
In any case, I think you need to be good at basic control theory to get it to work properly.
In principle, you could to some extent correct for the phase shift of the LC filter with an inverse filter after the ADC. Just make a digital minimum-phase filter that has an upward second-order slope from the frequency where the LC filter response starts to drop.
In any case, I think you need to be good at basic control theory to get it to work properly.
I see--I would like to make something performant above all else, though. I could always use a faster, low bit ADC, I'm just trying to get the same performance without paying for another chip. I came across the same problem with linear phase shortly after posting my response, so that's out the window. I'd like to stick to post-filter feedback or multiple feedback if possible because of the load-invariant properties thereof.I think functionality could be had if compromises in performance are made for example, by lowering the loop gain. Note that no SMPSs take feedback from before the filter but they're all still stable and functional.
Any filter adds to the delay in the loop to give the same consequences. For the pre-filter feedback case, the huge 180* phase shift of the LC filter is not present and therefore better stability is inherently possible. When you pull feedback after the filter, this 180* phase margin suddenly disappears.
Wouldn't that cause oscillation problems too, as it would decrease gain margin? That's something I'm lacking, I'm hoping to take a couple classes when I'm back at school and enlist the help of some professors and peers.Linear-phase filters have more phase shift than minimum-phase filters (the purely theoretical ones that predict the future excepted).
In principle, you could to some extent correct for the phase shift of the LC filter with an inverse filter after the ADC. Just make a digital minimum-phase filter that has an upward second-order slope from the frequency where the LC filter response starts to drop.
In any case, I think you need to be good at basic control theory to get it to work properly.
Couple possible things I found to increase stability:
Paper about distributing delay which could be accomplished by running both the Certus-NX's ADCs a couple pipeline cycles apart. I'm not too sure on this one's feasibility or effectiveness for this use case, but I found it interesting.
The second one is a 2nd order integrator configuration that adds some phase lead at higher frequencies. Top plot is just the integrator, red is output filter + delay, and blue is the two multiplied. Right now I have about 10db of gain margin, which can be adjusted. This seems too good to actually work though, like I'm having my cake and eating it too?
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