I will check them out and see... Since multiple traces appear even with the blanking signal present, you are probably correct that something is messing up the grid drive and/or the plate voltage.
Jaz
I'd suggest first looking at grid and plate signals to confirm they are coming out as expected. Also tracing both signals is key to look at the phase delay and ensure if your phase adjustment circuit is providing the necessary correction to put both signals in perfect sync. That will be the best way to eliminate the retrace.
If you can post your circuit it may be easier to help out
cheers
Ale
If you can post your circuit it may be easier to help out
cheers
Ale
Ale,
Looking at the grid drive and B+ supply lines, there appears to be some line interference, I can see a slow moving wave moving across the grid drive signal - I think this is causing the retrace. The interference is also clearly observable on the bias supply, even as the output of the 4520 going into Q1 remains pretty clean. So far, I have not been able to isolate the source of the interference, I have tried the following so far: pi ac-line filter, external DC bias supply (i.e., -80V on your schematic), DC filament supply, DC B+ supply.
I used your schematic, other than some minor changes to the no. of steps and volts/step functions, everything is pretty much the same.
Partial schematic:
https://dl.dropbox.com/u/1326040/Grid%20Driver.pdf
Short video showing the line interference:
https://dl.dropbox.com/u/1326040/MVI_1521.AVI
TIA,
Jaz
Looking at the grid drive and B+ supply lines, there appears to be some line interference, I can see a slow moving wave moving across the grid drive signal - I think this is causing the retrace. The interference is also clearly observable on the bias supply, even as the output of the 4520 going into Q1 remains pretty clean. So far, I have not been able to isolate the source of the interference, I have tried the following so far: pi ac-line filter, external DC bias supply (i.e., -80V on your schematic), DC filament supply, DC B+ supply.
I used your schematic, other than some minor changes to the no. of steps and volts/step functions, everything is pretty much the same.
Partial schematic:
https://dl.dropbox.com/u/1326040/Grid%20Driver.pdf
Short video showing the line interference:
https://dl.dropbox.com/u/1326040/MVI_1521.AVI
TIA,
Jaz
Jaz,
Looking at the video cleary two signs: grid clock is not in phase with anode sweep and also it may look like the PLL is not stable as there is some double tracing which may be the cause of frequency instability.
The grid driver (last mosfet) may need some protection in case you omit the grid resistor in case of a short.
To me, the phase sync issue was the biggest pain in this design. Have a close look at your PLL and phase adjustment circuit first. Everything comes very easy after that
Ale
Looking at the video cleary two signs: grid clock is not in phase with anode sweep and also it may look like the PLL is not stable as there is some double tracing which may be the cause of frequency instability.
The grid driver (last mosfet) may need some protection in case you omit the grid resistor in case of a short.
To me, the phase sync issue was the biggest pain in this design. Have a close look at your PLL and phase adjustment circuit first. Everything comes very easy after that
Ale
Jaz,
I agree with Ale's comments. I also found that my HV plate drive was much better if I used a simple full wave rectifier rather than the bridge and utilizing the HV transformer secondary center tap to connect the sensing resistor via ground. Also the grid stopper resistor is key for stability and a clear display of curves in some tubes.
Alfredo
I agree with Ale's comments. I also found that my HV plate drive was much better if I used a simple full wave rectifier rather than the bridge and utilizing the HV transformer secondary center tap to connect the sensing resistor via ground. Also the grid stopper resistor is key for stability and a clear display of curves in some tubes.
Alfredo
Thanks for the feedback. I will work on the PLL and the rectifiers this weekend and report back, it's good to have you guys guide me through it. 🙂
Thanks,
Jaz
Thanks,
Jaz
I took the cue from Merlin and stripped out the 4046 and 4017, so everything just syncs to the line. The results were much better, the image is steady (as it should) but I still have a small loop for each of the curves... Getting closer.
Jaz
Jaz
Jaz, good progress. I'd suggest you look at both anode and grid signals. Trigger the scope with the grid signal and look at frequency stability and phase. Once you can sync both signals you will then be in a good position to isolate the double tracing. If signals are in sync, it may be either the tube, the wiring or oscillation. Try testing a tube you know is in good shape and is gm is not that high.
Ale
Ale
Trouble-shooting Day 2
I don't have a center tap xfmr, but I have tried the bridge, half-wave and no rectification at all, they all showed the loop.😡
The grid drive and anode are quite clean and sync fine - no drift at all. I tried a few different tubes - same result (perhaps the loop size varied a bit), they were all pretty generic tubes - 12AX7 and 12AV7.
Please take a look at how my sense resistors are placed and see if they could cause the loops, especially the current sense. I think I also tried putting the current sense resistor from the cathode to ground a bit earlier, but had the same result, in any case, I like to have the cathode tied directly to ground, that's how Tektronix does it.
Sense resistors:
Grid drive and anode:
Curve sample:
https://dl.dropbox.com/u/1326040/IMG_1540_sm.jpg
Thanks,
Jaz
I don't have a center tap xfmr, but I have tried the bridge, half-wave and no rectification at all, they all showed the loop.😡
The grid drive and anode are quite clean and sync fine - no drift at all. I tried a few different tubes - same result (perhaps the loop size varied a bit), they were all pretty generic tubes - 12AX7 and 12AV7.
Please take a look at how my sense resistors are placed and see if they could cause the loops, especially the current sense. I think I also tried putting the current sense resistor from the cathode to ground a bit earlier, but had the same result, in any case, I like to have the cathode tied directly to ground, that's how Tektronix does it.
Sense resistors:
An externally hosted image should be here but it was not working when we last tested it.
Grid drive and anode:
An externally hosted image should be here but it was not working when we last tested it.
Curve sample:
https://dl.dropbox.com/u/1326040/IMG_1540_sm.jpg
Thanks,
Jaz
The steps on the grid drive do not look correct, they have to be completely flat. Right now you have a tri level on each step. The small level difference near the top of the plated drive would certainly cause a loop. Also the phase is off, this will also add to it.
Ok, I will try and clean it up, are you using coax cable to the grid? I am using a thin stranded cable only...
Jaz
I do not use coax. From what i can see from your previous picture it appears those level differences are not random, as if there is an issue either with your primary clock or the counter.
Isolate the counter from the rest of the circuit and measure clock signal there. I don't use coax either and my clock was very clean even in a breadboard. Twist grid signal cable with ground signal in a twisted pair to the socket. I added a ferrite bead as well.
Ale
Ale
Guys,
Thanks for the feedback, I won't have a chance to work on the project for a few weeks due to my travel schedule, will get back to it once I get back, I think it is getting pretty close. 🙂
Jaz
Thanks for the feedback, I won't have a chance to work on the project for a few weeks due to my travel schedule, will get back to it once I get back, I think it is getting pretty close. 🙂
Jaz
Had some free time on my road trip, so I was going over some of the pictures that I took of the tracer and noticed that the plate voltage and staircase waveforms are not like the way Merlin showed in his design. In his version (top graph in the attach picture), the peaks occur at the step transitions, but in mine they occur in the valleys, would that result in the double traces, I wonder?
Ale, if you can show me a shot of the waveform at the gate of the IRF9630 that would be great, since my design closely follows yours. Really like to get it working once I return from the road, and start to trace some curves! 🙂
TIA,
Jaz
Ale, if you can show me a shot of the waveform at the gate of the IRF9630 that would be great, since my design closely follows yours. Really like to get it working once I return from the road, and start to trace some curves! 🙂
TIA,
Jaz
An externally hosted image should be here but it was not working when we last tested it.
The stairs still do not look correct. Is the channel ac coupled or dc coupled? It should be DC coupled and the steps have to look completely flat. If the slant in the picture is real, it would cause the loop as the grid voltage is not the same at the same plate voltage, yielding a different plate current.
Jaz,
If you're sensing at the ground return as per Merlin's suggestion be careful of the ground loops including your scope when DC coupled. There are some grid-anode signal traces earlier In the thread.
As Alfredo says the grid steps should be clean and flat steps!
Ale
If you're sensing at the ground return as per Merlin's suggestion be careful of the ground loops including your scope when DC coupled. There are some grid-anode signal traces earlier In the thread.
As Alfredo says the grid steps should be clean and flat steps!
Ale
The steps were DC-coupled I believe, I will double-check... Ground loop is a real possibility as well, appreciate the pointers as usual.
Thanks,
Jaz
Thanks,
Jaz
Almost there...
Made some modifications to the gate drive circuit and managed to get rid of most of the loops, still not quite a straight line yet though, I also found that there is severe line interference during "business hours", I think the construction site down the street really mess up the AC grid somehow... So I can only run the tests either early morning or late at night 😡
Another thing, my current setup is completely exposed - basically no shielding, I am sure that also contributes to the "dirty lines", going to try and put it in a metal box to see that would improve things. Slowly getting there...🙂
The latest curves:
Jaz
Made some modifications to the gate drive circuit and managed to get rid of most of the loops, still not quite a straight line yet though, I also found that there is severe line interference during "business hours", I think the construction site down the street really mess up the AC grid somehow... So I can only run the tests either early morning or late at night 😡
Another thing, my current setup is completely exposed - basically no shielding, I am sure that also contributes to the "dirty lines", going to try and put it in a metal box to see that would improve things. Slowly getting there...🙂
The latest curves:
An externally hosted image should be here but it was not working when we last tested it.
Jaz
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