Distortion at frequencies above 500Hz???

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#22
cyaniccypher said:
I know the difference between propagation delay and dead time.
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Uhh, maybe check the model to verify it's behaving as intended? Might want to follow up on the suggestion from post 12 to have look at the high side behaviour while you're at it.

Since the schematic in post 10 doesn't reflect the board population my sim isn't particularly useful. I probably won't get time to revisit until next week.
 
#23
Had some time to get back to this. After correcting propagation delay, high and low side references, switch models, and missing or incorrect ESRs and ESLs in the power stage and including some best case layout parasitics I get 0.031% THD out of LTSpice. 0.022% of that occurs with ideal components (and fixing the switch models reduces THD by 0.011%). It's likely the layout model is optimistic and I've not plugged in supply considerations, EPCs, or signal side parasitics. I'd expect a more complete and accurate model to be within a few dB of the measured ~0.075% THD at 5kHz.
 
#24
twest820 said:
Had some time to get back to this. After correcting propagation delay, high and low side references, switch models, and missing or incorrect ESRs and ESLs in the power stage and including some best case layout parasitics I get 0.031% THD out of LTSpice. 0.022% of that occurs with ideal components (and fixing the switch models reduces THD by 0.011%). It's likely the layout model is optimistic and I've not plugged in supply considerations, EPCs, or signal side parasitics. I'd expect a more complete and accurate model to be within a few dB of the measured ~0.075% THD at 5kHz.
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Thank you so much for all the work. Would it be possible for you to post the final simulation so that i may learn from it.
 
#25
Beyond the suggestions made previously this thread I think the most useful thing would be to spend some time with Eva's posts. She knew more about class D in 2009 than I probably ever will. So I'd defer to her for an understanding of the design and implementation limitations which apply here.

I noticed another error in the switch models. So I added some minimal power stage supply modeling (probably more or less best case and hence optimistic) and reran the sim with the datasheet source current limit. 0.052% THD. The remaining 0.023% is likely explicable by better aligning the model to the actual layout and package inductances. And perhaps considering other factors not modeled such as mismatched propagation delays between the two Si8234s.
 
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