Hi all,
I want to build a digital equalizer with some additional signal processing capabilities.
The system consists of an ADC for analog input (perhaps the new 127dB AKM chip),
a DAC chip (PCM1792A or similar) and a SPDIF receiver chip.
At the heart is a Cortex-M4 or M7 ARM processor with 2x I2S interfaces and High-Speed USB.
The goal is a high-quality digital equalizer with room correction and other special signal processing.
The DAC output has a programable step-attenuator.
The board should support 48k and 44.1k sample rates (and multiples).
I need some help how to build a jitter free and simple clock system.
For analog input and output i could use a low jitter crystal oscillator, which is fine.
For USB input i can use an asynchronous design with the same low jitter crystal.
But for SPDIF input i must use a PLL, which is not so good regarding jitter.
The specified jitter performance of the SPDIF receiver chips is not so great,
(about 50-200ps) and i am looking for sime tricks to do it better.
I am looking for a simple system without mutch clock switching.
By the way, the ARM microcontroller has a audio PLL integrated
(without jitter specification)..
Do you have some ideas or helpful references how i can solve the clock problem without introducing jitter?
Thx, Udo
I want to build a digital equalizer with some additional signal processing capabilities.
The system consists of an ADC for analog input (perhaps the new 127dB AKM chip),
a DAC chip (PCM1792A or similar) and a SPDIF receiver chip.
At the heart is a Cortex-M4 or M7 ARM processor with 2x I2S interfaces and High-Speed USB.
The goal is a high-quality digital equalizer with room correction and other special signal processing.
The DAC output has a programable step-attenuator.
The board should support 48k and 44.1k sample rates (and multiples).
I need some help how to build a jitter free and simple clock system.
For analog input and output i could use a low jitter crystal oscillator, which is fine.
For USB input i can use an asynchronous design with the same low jitter crystal.
But for SPDIF input i must use a PLL, which is not so good regarding jitter.
The specified jitter performance of the SPDIF receiver chips is not so great,
(about 50-200ps) and i am looking for sime tricks to do it better.
I am looking for a simple system without mutch clock switching.
By the way, the ARM microcontroller has a audio PLL integrated
(without jitter specification)..
Do you have some ideas or helpful references how i can solve the clock problem without introducing jitter?
Thx, Udo
I don't think a Cortex M4 like a the STM F4 series microcontroller at 168Mhz is capable of executing complex signal chains like room correction, parametric equalizers ect... it does have a FPU and DMA channels for memory expansion (which you will need by the way) but most importantly it isn't a SIMD processor so you will run very quickly out of clock cycles as you chain signal blocks and run in multi-channel mode.
Dont take the above as gospel, I stand to be corrected I did see a company run a cortex M4 through some "basic" filtering and equalizers, the M4 can serve as a basic signal path for entry level "dspish" stuff
A serious route will be to use SHARC processors, even their old stuff like the 21065 66 Mhz core (which by the way im going to try and use as im also a dsp beginner like you) now this platform is fast and very well documented, pity the tools are sh** expensive for a beginner, im using a clone JTAG ICE.
Thanks for your links! I too think that the M4 is not as fast as a real DSP.
But it has some advantages too, as it allows a single chip solution (not counting ADC and DAC):
- LQFP 144 housing
- relative cheap high-speed USB interface
- Flash and RAM on-chip
I hope, that NXP will launch a Cortex M7 soon, compatible to the M4 LPC43xx series.
This will at least double the performance of the M4.
I put the emphasis here on a stereo digital equalizer. The equalizer will use parametrized biquad IIR filters mainly.
These filters are already very fast on the M4, as they do not need the advanced DSP features. With FIR filters the DSP has a strong advantage, but i found no DSP with High-Speed USB and FLASH/RAM on chip in a DIY friendly housing...
Anyway i want the high-speed USB interface. If more DSP power is needed i will put a dedicated DSP or FPGA chip on the PCB.
But it has some advantages too, as it allows a single chip solution (not counting ADC and DAC):
- LQFP 144 housing
- relative cheap high-speed USB interface
- Flash and RAM on-chip
I hope, that NXP will launch a Cortex M7 soon, compatible to the M4 LPC43xx series.
This will at least double the performance of the M4.
I put the emphasis here on a stereo digital equalizer. The equalizer will use parametrized biquad IIR filters mainly.
These filters are already very fast on the M4, as they do not need the advanced DSP features. With FIR filters the DSP has a strong advantage, but i found no DSP with High-Speed USB and FLASH/RAM on chip in a DIY friendly housing...
Anyway i want the high-speed USB interface. If more DSP power is needed i will put a dedicated DSP or FPGA chip on the PCB.
Hi,
Meantime i have sorted out the clock issue somewhat. The PCB will have two low jitter crystals (11.2896 and 12.288 MHz for 44.1 and 48 ks).
The USB interface will be asynchronous (= has no jitter besides the master clock jitter), and the SPDIF interface has a sample rate converter chip.
The new AK5397 ADC claims 127 dB SNR, and jitter induced SNR should be 10dB less. So jitter induced SNR should be less than 137 dB..
The SNR due to jitter is 20*log10(1/(2*pi*fs*t_jitter))]. This means that the master clock must have less than 1 ps rms jitter..
At the moment i am investigating a discrete oscillator based on Driscoll's low phase noise design, which can be switched between two crystals.
Has anyone done some real measurements on clock jitter? I read a lot of the "Well tempered master clock" thread, but nobody has posted some real jitter measurements...
Greetings,
Udo
Meantime i have sorted out the clock issue somewhat. The PCB will have two low jitter crystals (11.2896 and 12.288 MHz for 44.1 and 48 ks).
The USB interface will be asynchronous (= has no jitter besides the master clock jitter), and the SPDIF interface has a sample rate converter chip.
The new AK5397 ADC claims 127 dB SNR, and jitter induced SNR should be 10dB less. So jitter induced SNR should be less than 137 dB..
The SNR due to jitter is 20*log10(1/(2*pi*fs*t_jitter))]. This means that the master clock must have less than 1 ps rms jitter..
At the moment i am investigating a discrete oscillator based on Driscoll's low phase noise design, which can be switched between two crystals.
Has anyone done some real measurements on clock jitter? I read a lot of the "Well tempered master clock" thread, but nobody has posted some real jitter measurements...
Greetings,
Udo
@udok
Yes, as a micro-controller its a fantastic platform, lots of I/O and lots of peripherals with a FPU, its fast and you can use C without bothering to much about "optimizations" and more about the problem, oh and their are lots of open source IDE`s out there.
anyway back to the point,
The cortext M4 for a general purpose stereo parametrized biquad IIR? it can work for sure! havent tried it but im 100% it will work in fact there is a cortex m4 cmsis DSP library from arm to aid dsp development.
I use MATLAB to verify dsp code and algorithms.
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Hi, I'm totall new to DSP but have programmed C, kept libs fresh and so on... But DSP? I have this idea of creating a programmable parametric eq. 2-ch at this point. Where do I find the basics? Please.
Regards
Regards
STM already has the Cortext M7 circling around for certain venders commercial release is early next year,
https://www.youtube.com/watch?v=7YbGNp23j9w
http://www.arm.com/products/processors/cortex-m/cortex-m7-processor.php
Get hold of MATLAB and start learning to use the signal dsp stuff, lots of material on youtube on DSP various levels of complexity, you need something like MATLAB or Octave to learn it, you dont need to touch chips for now.
A quick filter reference is http://www.musicdsp.org/files/Audio-EQ-Cookbook.txt
https://ccrma.stanford.edu/~jos/filters/ has more information.
Unfortunately the STM32F7 does not have high-speed USB with integragted Phy. NXP and Atmels are to my knowledge the only Cortex M4 manufacturers of high-speed USB interfaces WITH integrated Phy.
The M4 has good 32 bit math with library support. The Biquad filter block is included in the DSP libraries.
Some marketing:
https://www.youtube.com/watch?feature=player_embedded&v=15l8TIEaOHo
https://ccrma.stanford.edu/~jos/filters/ has more information.
Unfortunately the STM32F7 does not have high-speed USB with integragted Phy. NXP and Atmels are to my knowledge the only Cortex M4 manufacturers of high-speed USB interfaces WITH integrated Phy.
The M4 has good 32 bit math with library support. The Biquad filter block is included in the DSP libraries.
Some marketing:
https://www.youtube.com/watch?feature=player_embedded&v=15l8TIEaOHo
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At the moment i would really appreciate some hard facts about clock jitter of integrated CMOS xtal oscillators.
Is it ok for best audio quality to use the integrated oscillators and multiplexers of the AK4115?
Can anybody comment on this?
Is it ok for best audio quality to use the integrated oscillators and multiplexers of the AK4115?
Can anybody comment on this?
The crystal oscillators in the AK4117 are only used when it is the clock master. When it is receiving SPDIF from another source, it uses an integrated PLL the same as every other SPDIF receiver in the world. The datasheet quotes an RMS jitter of about 100ps for this, which is pretty good.
The WM8804 is supposed to have a "jitter scrubbing architecture" and claims 50ps RMS jitter.
A good crystal oscillator can have about 1ps of jitter at 100MHz; Converting Oscillator Phase Noise to Time Jitter | DigiKey
The smallest amount of jitter that has ever been shown to be audible is about 30ns.
The WM8804 is supposed to have a "jitter scrubbing architecture" and claims 50ps RMS jitter.
A good crystal oscillator can have about 1ps of jitter at 100MHz; Converting Oscillator Phase Noise to Time Jitter | DigiKey
The smallest amount of jitter that has ever been shown to be audible is about 30ns.
I will put something together and listen and measure how sound it is
But 50 ps seems too much for a 127 dB ADC according to the formula given in the link by scopeboy.
A perfect ADC with 50 ps jitter results in 110 dB SNR @ 10 kHz.
30ns is audible, as the SNR would be reduced to 55 dB @ 10 kHz and 75 dB @ 1k Hz - less than CD quality.
I see not mutch sense in using a high performance ADC with a clock system with more than 1-2 ps jitter - or do i miss something?
But 50 ps seems too much for a 127 dB ADC according to the formula given in the link by scopeboy.
A perfect ADC with 50 ps jitter results in 110 dB SNR @ 10 kHz.
30ns is audible, as the SNR would be reduced to 55 dB @ 10 kHz and 75 dB @ 1k Hz - less than CD quality.
I see not mutch sense in using a high performance ADC with a clock system with more than 1-2 ps jitter - or do i miss something?
Audio has to be degraded well below CD quality before the degradation is audible.
Many sigma-delta converters are designed with a certain amount of jitter rejection. Jitter on MCLK partly averages out, so the SNR is not degraded quite as much as the formula in my link would suggest. This appnote Analyzing Audio DAC Jitter Sensitivity - Application Note - Maxim relates to Maxim DACs, but any good DAC manufacturer should be able to give you something similar.
Many sigma-delta converters are designed with a certain amount of jitter rejection. Jitter on MCLK partly averages out, so the SNR is not degraded quite as much as the formula in my link would suggest. This appnote Analyzing Audio DAC Jitter Sensitivity - Application Note - Maxim relates to Maxim DACs, but any good DAC manufacturer should be able to give you something similar.
Thanks for the link to the Maxim Application Note! This is a real evidence that SNR reduction due to jitter can be meaningful predicted by the simple formula 20*log10(1/(2*pi*f0*t_jitter)).
Figure 10 and 11 are in good agreement (+-6dB).
Even the claimed jitter reduction does not cope well with random noise jitter!
The formula predicts 63 dB THD+N for Fig 11 and the measurement shows 70 dB.
The competitor 3 DAC is an extrapolation because this DAC was not stable with the jitter clock (But competitor 3 DAC is in good agreement with the 88 dB prediction in Fig 10).
AP TN 23 has more information on jitter - but it is not easy to read...
http://www.audiophilleo.com/zh_hk/docs/Dunn-AP-tn23.pdf
And wake up - we are living in 2014 and nobody anymore associates a 75 dB DAC with high fidelity🙂
Figure 10 and 11 are in good agreement (+-6dB).
Even the claimed jitter reduction does not cope well with random noise jitter!
The formula predicts 63 dB THD+N for Fig 11 and the measurement shows 70 dB.
The competitor 3 DAC is an extrapolation because this DAC was not stable with the jitter clock (But competitor 3 DAC is in good agreement with the 88 dB prediction in Fig 10).
AP TN 23 has more information on jitter - but it is not easy to read...
http://www.audiophilleo.com/zh_hk/docs/Dunn-AP-tn23.pdf
And wake up - we are living in 2014 and nobody anymore associates a 75 dB DAC with high fidelity🙂
I don't think human hearing has improved much since the 1980s. Also vinyl has worse than 75dB SNR and it is supposed to sound better than digital. 😉
There is no evidence that the 50-100ps of jitter introduced by a SPDIF receiver vs. a quartz oscillator with 1ps of jitter is audible, so I think you are just playing the numbers game for the sake of it. No harm in doing this, except that reclocking a SPDIF input against a low jitter oscillator greatly increases the cost and complexity of the system, so you are also throwing away money for the sake of it.
There is no evidence that the 50-100ps of jitter introduced by a SPDIF receiver vs. a quartz oscillator with 1ps of jitter is audible, so I think you are just playing the numbers game for the sake of it. No harm in doing this, except that reclocking a SPDIF input against a low jitter oscillator greatly increases the cost and complexity of the system, so you are also throwing away money for the sake of it.
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You are right that human hearing has not improved since 1980 🙂 There may be even recordings, which sound spiritless without the background hiss and distortion.
But the question was how much jitter is acceptable in a clocking system for an digital equalizer and how such a clocking sytem could be designed without compromizing the ADC/DAC performance with minimum effort.
The SNR is more important in an equalizer, as you need about 18 dB headroom for the analog input peaks and the EQ should not compromize the analog SNR.
If you have 75 dB ADC/DAC and +4 dBu is -18 dB FS, your noise level is -53 dBu or 1.7 mV RMS... which is far worse than a typical analog noise level of -100 dBu.
But the question was how much jitter is acceptable in a clocking system for an digital equalizer and how such a clocking sytem could be designed without compromizing the ADC/DAC performance with minimum effort.
The SNR is more important in an equalizer, as you need about 18 dB headroom for the analog input peaks and the EQ should not compromize the analog SNR.
If you have 75 dB ADC/DAC and +4 dBu is -18 dB FS, your noise level is -53 dBu or 1.7 mV RMS... which is far worse than a typical analog noise level of -100 dBu.
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