Well, the best way is to derive the ADC and DAC's MCLK directly from a good quality crystal oscillator.
The problem with this approach is that you can't lock an ordinary crystal oscillator to an external clock source, so you can't use your system with a digital input from a SPDIF or adaptive USB receiver. (An asynchronous USB receiver can be slaved to a crystal, but that doesn't solve the SPDIF problem.)
There are 2 ways of getting round this: you can use an asynchronous sample rate converter to resample the digital input data onto your local clock (I wonder how good the jitter rejection is on these?) or you can use a voltage-controlled crystal oscillator (VCXO) tuned by a PLL, to follow the average sample rate of the source while filtering out jitter. The crystal has a very high Q factor that makes it extremely effective at this. The downside is that the tuning range is limited, so it might fail to lock to some sources that have an inaccurate sample rate.
I believe the Schiit Gungnir DAC uses the VCXO, as well as some Focusrite pro audio ADCs. If I were building a super low jitter DAC myself, I would also choose a VCXO. However in practice I probably couldn't build one for the price of the Gungnir.
The problem with this approach is that you can't lock an ordinary crystal oscillator to an external clock source, so you can't use your system with a digital input from a SPDIF or adaptive USB receiver. (An asynchronous USB receiver can be slaved to a crystal, but that doesn't solve the SPDIF problem.)
There are 2 ways of getting round this: you can use an asynchronous sample rate converter to resample the digital input data onto your local clock (I wonder how good the jitter rejection is on these?) or you can use a voltage-controlled crystal oscillator (VCXO) tuned by a PLL, to follow the average sample rate of the source while filtering out jitter. The crystal has a very high Q factor that makes it extremely effective at this. The downside is that the tuning range is limited, so it might fail to lock to some sources that have an inaccurate sample rate.
I believe the Schiit Gungnir DAC uses the VCXO, as well as some Focusrite pro audio ADCs. If I were building a super low jitter DAC myself, I would also choose a VCXO. However in practice I probably couldn't build one for the price of the Gungnir.
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A more common, third method of clock matching is to steer the divider in a fractional DPLL. This is done with about a 10kHz PLL bandwidth in the CS8416 and about 1Hz in the WM8804/5. I would also encourage folks on this thread to check out Cirrus AN-339 and Wolfson's white papers on SPDIF receive; the specifications discussed so far aren't really the most useful way of distinguishing between audible and inaudible jitter. (For clock matching there is also the sample and hold block in the AD1955 and the slightly more sophisticated implementation used in ESS DACs.)
ASRCs have infinite jitter rejection. Most implementations do, however, inject other errors which are probably worse than the terms associated with PLL tracking, though I'm not aware of any rigorous studies. Start, oh, here for recent discussion about that.
A related difficulty is system gain structure is rarely controlled for in jitter audibility assessments. The common configuration of digital volume and excessive power amplifier gain demands perhaps an order of magnitude lower time error at the DAC than might strictly be necessary.
ASRCs have infinite jitter rejection. Most implementations do, however, inject other errors which are probably worse than the terms associated with PLL tracking, though I'm not aware of any rigorous studies. Start, oh, here for recent discussion about that.
Interesting. Do you happen to have a reference? I've seen claims as little as 5ps can be audible, though the methods used seem a bit dodgy. I think it was in this talk Martin Mallinson mentions ESS found less than 1ns to be audible, though the remark is made in passing.
A related difficulty is system gain structure is rarely controlled for in jitter audibility assessments. The common configuration of digital volume and excessive power amplifier gain demands perhaps an order of magnitude lower time error at the DAC than might strictly be necessary.
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One must also realize that many articles, like the one linked in post #15, relates to jitter *above* 10khz, i.e. not really what we listen to. So if this is the bw in which the time error is specifyed i.e. 1,9 ps if measured between fs +10khz and > this figure does not tell the whole important story. What about say 5hz - 10 kHz - what is the timing error here?
This is of course if one believes that that the spectral distribution of the timing error in the clock driving the D/A conversion has immediate impact on the corresponding frequency of music signal. I do.
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This is of course if one believes that that the spectral distribution of the timing error in the clock driving the D/A conversion has immediate impact on the corresponding frequency of music signal. I do.
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Check out AN-339's definition of baseband jitter. You may also find Audio Precision's Technote 23 of interest from page 10 on.
Equivalent information for parts like the AK4136 and AK4137 isn't documented, so they'd have to be measured. Per ESS's policies I probably shouldn't mention specifics. But, basically, the way their parts are set up is the loop bandwidth defaults substantially below 1Hz and can be increased if lock problems occur. The loop rolloff's undocumented but, for jitter rejection, the implementation's likely best in class. Downside is ESS's default antialiasing filters were nothing special last I checked, though at least it's possible to get away from brickwall and, with certain parts, program one's own coefficients.
To answer the OP's question, I'd say the main options are 1) Wolfson SPDIF receiver + any DAC or 2) try to figure out how good AKM's recently released ASRCs are.
I phrased this poorly; infinite rejection would require infinite mathematical precision and no loop bandwidth (meaning the average input and output frequency would have to be known a priori). The limitation is the loop as getting the bits for 140+dB is no problem. For example, the AD1896 in slow mode has a 3Hz bandwidth falling at 40dB/decade versus 1Hz at (so far as I know) 20dB/decade in the WM8804/5. So, depending on the jitter spectra and whether fast or slow mode is selected, the AD1896 might or might not provide more source jitter rejection than the Wolfson PLLs. When I've sketched through some typical maths the answer's been it's not compelling enough for me to select the part (as an aside, the SigmaDSP parts reuse the AD1896 ASRC block but don't expose the loop bandwidth control).
Equivalent information for parts like the AK4136 and AK4137 isn't documented, so they'd have to be measured. Per ESS's policies I probably shouldn't mention specifics. But, basically, the way their parts are set up is the loop bandwidth defaults substantially below 1Hz and can be increased if lock problems occur. The loop rolloff's undocumented but, for jitter rejection, the implementation's likely best in class. Downside is ESS's default antialiasing filters were nothing special last I checked, though at least it's possible to get away from brickwall and, with certain parts, program one's own coefficients.
To answer the OP's question, I'd say the main options are 1) Wolfson SPDIF receiver + any DAC or 2) try to figure out how good AKM's recently released ASRCs are.
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