More questions :
To make use of the differential output, the transmission lines between the AD9687 and the MC10125s should be connected by twinax cables with matched impedance (if the length is say longer than 25mm to justify running them on the PCB).
Any idea what cable to use (that is available on the open market) ?
Thx again,
Patrick
To make use of the differential output, the transmission lines between the AD9687 and the MC10125s should be connected by twinax cables with matched impedance (if the length is say longer than 25mm to justify running them on the PCB).
Any idea what cable to use (that is available on the open market) ?
Thx again,
Patrick
Yes, but it has no differential outputs.
The new version is a tiny bit faster.
If you want the chip, send me a PM.
I will just use self made cables of equal length with SMB plugs. I think it is RG179.
If the cable gets long, it might be better to use a line receiver before the translator. I am not sure....
According to the datasheet I downloaded from AD, the 96687 has balanced output as well.
I do want to use SMD for shorter signal path, so I shall use the new chip.
Many thanks for the offer, and for sharing.
Pls keep us posted.
Patrick
I do want to use SMD for shorter signal path, so I shall use the new chip.
Many thanks for the offer, and for sharing.
Pls keep us posted.
Patrick
I meant the 8561.
Please report here when you have built it.
You can play with the AD input resistors 1k to 100k and see if it makes any difference for you.
I found a 2N5912 could be nice for the oscillator...
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It will take a while, as I have to redo the entire architecture of the SD player. The ECL needs dual 5V supply, which is also extra work. I shall most likely be using BF862 instead of 2SK152, and I want to go entirely SMD for the clock. Still undecided whether to run the sine wave on transmission line to the dsPIC (i.e. before the AD96687), or run square wave over cable instead. If you use SMB and coax, you would need to run 2 wires per signal ??
But really nice idea. I like it. Please keep us informed of your progress.
Patrick
But really nice idea. I like it. Please keep us informed of your progress.
Patrick
The ECL reclocker works and is put into service 
It sounds ultimately transparent, smooth and relaxed, bla-bla-bla, so CMOS is out.
To push it to the limit, the next upgrade will be another faster ECL comparator to match the speed of the flipflop.
10E1651 has a bandwith > 1 GHz, 775 ps tpg and a rise time of 350 ps.
It sounds ultimately transparent, smooth and relaxed, bla-bla-bla, so CMOS is out.
To push it to the limit, the next upgrade will be another faster ECL comparator to match the speed of the flipflop.
10E1651 has a bandwith > 1 GHz, 775 ps tpg and a rise time of 350 ps.
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Firstly Happy New Year to all.
> It sounds ultimately transparent, smooth and relaxed, bla-bla-bla, so CMOS is out.
Your DAC still has CMOS data input, I guess ??
I spent quite a bit of time over Christmas looking into the whole clocking and logic scheme that I might need in a SD Player. And I shall publish my findings in a few days.
But basically, almost all ECL chips has jitter below 1ps (cycle to cycle), with the exception of conversion from ECL to TTL, which is quoted as 35ps (datasheet MC10ELT21, still excellent). Conversion to 5V CMOS has to be first ECL-TTL and then to CMOS using 74ACT1G50, which is complicated and probably poor performance. 3.3V CMOS is slight better as logic level is same as LVTTL. The ECL D-FFs are quoting 1ps cycle to cycle, but the propagation delay is 500ps, so I find 1ps long-term repeatability out of 500ps hard to believe. Maybe cycle-to-cycle, yes, but these chips are typically tested at 100MHz, so the jitter in the audio band would be quite different.
Still, it is easily a factor of 10 better than anything else. So I am still very tempted. The expense is considerable. I would need almost 100Euro extra chips, plus additional PSUs, ....., etc., plus a much more complicated PCB layout overall. But ground bounce I can almost ignore, so can I with cable length for ECL data / CLK.
BTW I am planning to use differential PECL for everything (clock and data). Comparator is ADCMP567, Reclocker is MC10EP29, Clock Buffer is ADCLK925 or MC10EL11, ...., etc.
Patrick
> It sounds ultimately transparent, smooth and relaxed, bla-bla-bla, so CMOS is out.
Your DAC still has CMOS data input, I guess ??
I spent quite a bit of time over Christmas looking into the whole clocking and logic scheme that I might need in a SD Player. And I shall publish my findings in a few days.
But basically, almost all ECL chips has jitter below 1ps (cycle to cycle), with the exception of conversion from ECL to TTL, which is quoted as 35ps (datasheet MC10ELT21, still excellent). Conversion to 5V CMOS has to be first ECL-TTL and then to CMOS using 74ACT1G50, which is complicated and probably poor performance. 3.3V CMOS is slight better as logic level is same as LVTTL. The ECL D-FFs are quoting 1ps cycle to cycle, but the propagation delay is 500ps, so I find 1ps long-term repeatability out of 500ps hard to believe. Maybe cycle-to-cycle, yes, but these chips are typically tested at 100MHz, so the jitter in the audio band would be quite different.
Still, it is easily a factor of 10 better than anything else. So I am still very tempted. The expense is considerable. I would need almost 100Euro extra chips, plus additional PSUs, ....., etc., plus a much more complicated PCB layout overall. But ground bounce I can almost ignore, so can I with cable length for ECL data / CLK.
BTW I am planning to use differential PECL for everything (clock and data). Comparator is ADCMP567, Reclocker is MC10EP29, Clock Buffer is ADCLK925 or MC10EL11, ...., etc.
Patrick
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> How is that board in terms of EMI and noise?
That is precisely the reason to use differential ECL. Please google.
Patrick
That is precisely the reason to use differential ECL. Please google.
Patrick
I don't know which DAC you use but the PCM56 datasheet does not say anything about CMOS, however it states that the inputs are both TTL & CMOS compatible.
But you are right, the question is how much is the performance limited by the DAC chip itself...
I checked DC levels in datasheets and there is > 100 mV overdrive.
So 10125 can drive PCM56 directly, no additional translators required.
The 4 x 10125 serve as translator, distributor and buffer for 4 x 8 DAC chips.
Fanout is 10 TTL loads and each data or serial clock output drives 8 DAC inputs, each LE output drives 4 DAC inputs.
I had worried much more for the 10124 because it is not recommended to directly convert from CMOS to ECL, but for TTL to ECL, anyway it works...
Where did you find the jitter spec for the ELT21 ? My datasheet states TBD.
ELT21 is quiet slow: 2 - 5,5 ns pgd.
10H125 seems faster: 0,85 - 3,35 ns pgd.
This ECL reclocker is my first prototype, only ICs from my collection used, I might upgrade later.
I wish also a happy new year to you all.
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Still, I don't know where you got the 35 ps from.
PECL is power supply sensitive.
You might need a very clean psu.
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http://www.onsemi.com/pub_link/Collateral/MC100ELT23-D.PDF
Page 3, Table 6, Random Clock Jitter 35ps typical.
> PECL is power supply sensitive.
Not when you use differential signals.
Patrick
Page 3, Table 6, Random Clock Jitter 35ps typical.
> PECL is power supply sensitive.
Not when you use differential signals.
Patrick
OK, that wasn't clear from the picture.
Patrick, I used PECL at my day job so I am just remembering some scope investigations, on a board with SMD and controlled layers. It doesn't hurt to be cautious and design conservatively.
> Patrick, I used PECL at my day job .....
Maybe you can share a few design tricks with us ?
Patrick
Maybe you can share a few design tricks with us ?
Patrick
Ok, I just remembered reading that in an ONSemi appl. note.
The EL31 is much faster - 2,8 GHz - but unfortunately not differential.
For my final reclocker, I am not sure wether I should have the preference on differential design or speed.
Also ONSemi has live chat with their experts available on their website.
When in doubt... They help you out.
My next target is elimination of the translator chip.
Perhaps with some tricks the DAC chips will reliably switch directly from PECL.
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