Given half-decent ventilation it doesn't happen.classd4sure said:
We stumbled onto it only because a customer had decided, against all advice, that "digitaru ampurifaia have no dissipation" and put 5x100W into a box that had effectively no ventilation. The top cover was made of a kind of lamination that insulated very well.
Then they started complaining that there was "thermal runaway" at 5x10W. It turned out that this happened only when the air temperature in the box hit 80 degrees. The module spec to which they agreed said that the ambient temperature should remain below 55 degrees. Thus the complaint was basically that "when we use the modules out of spec we get problems". Yeah.
Anyway we changed the clamp circuit to have them off our backs. One more happy customer.
Proper selection of mosfets has to do with evaluating the ratio of the gate charges. More specifically, Qgd/Qgs1 where Qgs1 is input charge accumulated before Vth.
Some data sheets include it, but the ones that do of course have it at a specific input voltage which may not lend to direct comparison with other mosfets/data sheets.
Therefore it seems best to use the capacitances as read from the graphs, as Crss (Cgd) is highly voltage dependant. OFten the graph doesn't go up to full supply, sometimes 80% of rated Vds but not always even that much. Crss keeps dropping with increasing voltage though, so you end up a worst case ratio, which is fine.
The ratio of these charges needs to be as low as possible in order to prevent Cdv/dt induced turn on. If its' greater than 1, there will be spurrious turn on! So aim for 1 or ideally less.
Fairchild does have a wide range of FETs to choose from with reduced miller charge which gives nice low ratio's, I think that's why our "Pro's" like them. They also have a decent parametric search which speeds things up a bit. EDIT: .....and free samples
A nice one I found is:
http://www.fairchildsemi.com/pf/FD/FDP3682.html
For which I calculated the "CR" ratio to be 0.57!
There is a pspice model of it available, which I've tried in the circuit, and it gives numerous errors which backing off rel tol and increasing iteration limit to 100.....crazy values.....does not help.
If you take a look at their subcircuit for it, it's not very surprising why it won't work. Seems they were pushing the limits of a mosfet model but didnt' make the effort to make sure it worked ok. I've had it simulate a few switches at best and it showed 0 shoot through, but....values were backed off so much I woulnd't rely on em at all anyway.
I made myself a ratio calculator in excel to make the job of comparing fets a little quicker for a given application, so later on I'll try finding one with a decent model.
The exact formula I used is:
Qgd/Qgs1 = (Cgd*(Vds-Vth))/(Cgs*Vth)
Again, read the capacitance values off of the graph and aim for a ratio less than 1.
Other ways of controlling Cdv/dt turn on are high current drive, which we dont' have here, higher Vth, negative gate drive, Higher Ron which we don't want...So you see this is really the only option we have to limit cross conduction to safe values or eliminate it all together.
Regards,
Chris
Some data sheets include it, but the ones that do of course have it at a specific input voltage which may not lend to direct comparison with other mosfets/data sheets.
Therefore it seems best to use the capacitances as read from the graphs, as Crss (Cgd) is highly voltage dependant. OFten the graph doesn't go up to full supply, sometimes 80% of rated Vds but not always even that much. Crss keeps dropping with increasing voltage though, so you end up a worst case ratio, which is fine.
The ratio of these charges needs to be as low as possible in order to prevent Cdv/dt induced turn on. If its' greater than 1, there will be spurrious turn on! So aim for 1 or ideally less.
Fairchild does have a wide range of FETs to choose from with reduced miller charge which gives nice low ratio's, I think that's why our "Pro's" like them. They also have a decent parametric search which speeds things up a bit. EDIT: .....and free samples
A nice one I found is:
http://www.fairchildsemi.com/pf/FD/FDP3682.html
For which I calculated the "CR" ratio to be 0.57!
There is a pspice model of it available, which I've tried in the circuit, and it gives numerous errors which backing off rel tol and increasing iteration limit to 100.....crazy values.....does not help.
If you take a look at their subcircuit for it, it's not very surprising why it won't work. Seems they were pushing the limits of a mosfet model but didnt' make the effort to make sure it worked ok. I've had it simulate a few switches at best and it showed 0 shoot through, but....values were backed off so much I woulnd't rely on em at all anyway.
I made myself a ratio calculator in excel to make the job of comparing fets a little quicker for a given application, so later on I'll try finding one with a decent model.
The exact formula I used is:
Qgd/Qgs1 = (Cgd*(Vds-Vth))/(Cgs*Vth)
Again, read the capacitance values off of the graph and aim for a ratio less than 1.
Other ways of controlling Cdv/dt turn on are high current drive, which we dont' have here, higher Vth, negative gate drive, Higher Ron which we don't want...So you see this is really the only option we have to limit cross conduction to safe values or eliminate it all together.
Regards,
Chris
Hi Chris,
shoot through it's rather shameful efficiency, but aren't always deadly for fet (danger edge is quite thin yet). When i tried some new driver/fet chain, i has put in serial with drain res about .33-1ohm, to avoid fet killing and for shoot through current monitoring. BTW, fet's explosions is beautiful show, if your PS allow it 🙂
ps: why you needed the 32A fet? Maybe 10-15 enough?100w?
ps1: FQP13N10?
shoot through it's rather shameful efficiency, but aren't always deadly for fet (danger edge is quite thin yet). When i tried some new driver/fet chain, i has put in serial with drain res about .33-1ohm, to avoid fet killing and for shoot through current monitoring. BTW, fet's explosions is beautiful show, if your PS allow it 🙂
ps: why you needed the 32A fet? Maybe 10-15 enough?100w?
ps1: FQP13N10?
Hi Ivan,
That's a good way to check for shoot through/measure it.
Why 32 amps? No good reason at all 😉 Really it was just an example of a mosfet that should do the job nicely.
However SOA is through the roof, and should we end up with modular pcb's with a seperate output stage, the same stage will work for much greater power levels into much lower loads, so it would likely be a great mosfet with that in mind.
I am not sold on it though, I would really like to find one with a working model, still having a CR ratio of less than 1. I'll be sure to check out the one you mentioned as well. I made that calculator to be able to more quickly evaluate one mosfet against the other, the one I suggested was actually the first I found with a decent ratio + spice model. Too bad the model doesn't seem to work at all, it takes a bit of effort to import them and change the symbol etc....I wasn't amused when I couldn't get it to work. I saw the subcircuit for it and thought to myself "this will certainly slow down the simulation a fair bit" never assuming they'd release a model that can't be simulated.
That's a good way to check for shoot through/measure it.
Why 32 amps? No good reason at all 😉 Really it was just an example of a mosfet that should do the job nicely.
However SOA is through the roof, and should we end up with modular pcb's with a seperate output stage, the same stage will work for much greater power levels into much lower loads, so it would likely be a great mosfet with that in mind.
I am not sold on it though, I would really like to find one with a working model, still having a CR ratio of less than 1. I'll be sure to check out the one you mentioned as well. I made that calculator to be able to more quickly evaluate one mosfet against the other, the one I suggested was actually the first I found with a decent ratio + spice model. Too bad the model doesn't seem to work at all, it takes a bit of effort to import them and change the symbol etc....I wasn't amused when I couldn't get it to work. I saw the subcircuit for it and thought to myself "this will certainly slow down the simulation a fair bit" never assuming they'd release a model that can't be simulated.
Hi Ivan,
I just evaluated the FQP13N10, here is what I found.
The CR (charge ratio) is very high! By looking at the charge graph you can see from Time 0 to the time it reaches V tresh there is 1nC on Qgs, and about 5nC accumulated "miller" charge on Qgd. This leaves a charge ratio of 5.
I also evaluated by looking at capacitance graphs and calculating charges (equation I had posted) and got 11.5. This leads me to believe it will be a monster for shoot through, and with the lower SOA of it ....I dont' think it would last long at all.
You are right though this is more along the lines of the current required, but if I find one that can handle a 100amps even I see no reason why it shouldnt' be used if it meets all other criteria. Would cost be any different for a higher current device? I'll be using the free samples anyway.. 😀
Best Regards,
Chris
I just evaluated the FQP13N10, here is what I found.
The CR (charge ratio) is very high! By looking at the charge graph you can see from Time 0 to the time it reaches V tresh there is 1nC on Qgs, and about 5nC accumulated "miller" charge on Qgd. This leaves a charge ratio of 5.
I also evaluated by looking at capacitance graphs and calculating charges (equation I had posted) and got 11.5. This leads me to believe it will be a monster for shoot through, and with the lower SOA of it ....I dont' think it would last long at all.
You are right though this is more along the lines of the current required, but if I find one that can handle a 100amps even I see no reason why it shouldnt' be used if it meets all other criteria. Would cost be any different for a higher current device? I'll be using the free samples anyway.. 😀
Best Regards,
Chris
ok Chris,
my calculation for FQP13N10 by your formula are Qgd/Qgs1=0.9, but even it's would be 11, saying that Cgs=35pf, (345pf instead).. and why it's worse? Cgd just a 20pf, i'm sure will not be problem to remove transient by p-BJT in UcD driver (we can control dv/dt choice Rgate>0). BTW, IRF540N gives 0.43!! Wanna try IRF540N vs FQP13N10?
my calculation for FQP13N10 by your formula are Qgd/Qgs1=0.9, but even it's would be 11, saying that Cgs=35pf, (345pf instead).. and why it's worse? Cgd just a 20pf, i'm sure will not be problem to remove transient by p-BJT in UcD driver (we can control dv/dt choice Rgate>0). BTW, IRF540N gives 0.43!! Wanna try IRF540N vs FQP13N10?
Hi Ivan,
You picked out my mistake exactly!
I entered 35pF instead of 335pF! Sorry.
So Ciss=335pf, I'll change it to 345pF since it's what you used.
Crss=Cgd=10pF, I'll change to 20 since it's what you used..(the graphs dont' make this very exact so it doesn't matter) Now I'll redo it.
Cgs=Ciss-Crss=345pF-20pF=325pF
Cgd=20pF
Qgd/Qgs1 = (Cgd*(Vds-Vth))/(Cgs*Vth)
=(20pF*(60-2))/(325pF*2)
=1.8
AAAAhhhh that's alot better than 11.5, yet still greater than 1 so it wont' be immune to Cdv/dt turn on. You got 0.9, must have used 30V for the calculation. The reason I used 60 is because with +-30V rails the mosfets see the full sixty during switching. I also took that into account with the original capacitance values I guesstimated from the graph.
Thanks for catching my stupid mistake, my little calculator is infallable, but I certainly am not.
I also agree that other things can be done to to help with spurrious turn on should it occur. Increasing Ron of the driver is one, but how high can it go before it can no longer fully enhance the mosfet? Using a high current, Cmos gate drive is another, or any that can pull Vgs to zero, or lower...making it more immune to the gate step voltage. The step will still be there but it won't matter. Still, the lower ratio the better. The FQP13N10 also has a rather high RdsOn doesn't it?
Anyway, It certainly isn't my intention to argue over which is the best mosfet, I just want to help people know how to choose one that will work well.
I haven't taken the time to check out any others yet because ......it's time I got to hear this thing...so I'm searching for parts to bubblegum one together. 2n3904's 2n3906's, 1n914 diodes, IRF511 (I don't even care about CR with this prototype enough to check the Charge Ratio, let it smoke I say!!!) 7812cv 12v 1.5amp linear regulator for the floating driver power supply, 24VA transformer lol.... need a full bridge and some filter caps, all destined for a plastic protoboard. I still need some caps. I found a nice 100ohm pot from the left/right balance of an old radio I smashed apart with a hammer yesterday, and I took some of the rest off of a 500$ micro controller I'll never use again. Wish me luck.
Regards,
Chris
You picked out my mistake exactly!
I entered 35pF instead of 335pF! Sorry.
So Ciss=335pf, I'll change it to 345pF since it's what you used.
Crss=Cgd=10pF, I'll change to 20 since it's what you used..(the graphs dont' make this very exact so it doesn't matter) Now I'll redo it.
Cgs=Ciss-Crss=345pF-20pF=325pF
Cgd=20pF
Qgd/Qgs1 = (Cgd*(Vds-Vth))/(Cgs*Vth)
=(20pF*(60-2))/(325pF*2)
=1.8
AAAAhhhh that's alot better than 11.5, yet still greater than 1 so it wont' be immune to Cdv/dt turn on. You got 0.9, must have used 30V for the calculation. The reason I used 60 is because with +-30V rails the mosfets see the full sixty during switching. I also took that into account with the original capacitance values I guesstimated from the graph.
Thanks for catching my stupid mistake, my little calculator is infallable, but I certainly am not.
I also agree that other things can be done to to help with spurrious turn on should it occur. Increasing Ron of the driver is one, but how high can it go before it can no longer fully enhance the mosfet? Using a high current, Cmos gate drive is another, or any that can pull Vgs to zero, or lower...making it more immune to the gate step voltage. The step will still be there but it won't matter. Still, the lower ratio the better. The FQP13N10 also has a rather high RdsOn doesn't it?
Anyway, It certainly isn't my intention to argue over which is the best mosfet, I just want to help people know how to choose one that will work well.
I haven't taken the time to check out any others yet because ......it's time I got to hear this thing...so I'm searching for parts to bubblegum one together. 2n3904's 2n3906's, 1n914 diodes, IRF511 (I don't even care about CR with this prototype enough to check the Charge Ratio, let it smoke I say!!!) 7812cv 12v 1.5amp linear regulator for the floating driver power supply, 24VA transformer lol.... need a full bridge and some filter caps, all destined for a plastic protoboard. I still need some caps. I found a nice 100ohm pot from the left/right balance of an old radio I smashed apart with a hammer yesterday, and I took some of the rest off of a 500$ micro controller I'll never use again. Wish me luck.
Regards,
Chris
It makes some sense to me as being the gate threshold voltage since if is higher, the mosfet resists turning on more with increasing drain voltage.
Hello,
Most welcome!
As I understand it yeah the miller plateau is the region where the mosfet is working in a linear state so it's easy to see it as being Vth as that's when voltage starts dropping over the mosfet. However they always say 2 to 4 volts for Vth, and the plateau voltage level is always higher, up around 5 ~ 7 volts.
According to the app notes I've read Vth occurs as soon as Cgs is charging, at which point the drain current starts to flow and increases more as Cgs is charged more. Once Cgs is fully charged, it starts charging the miller capacitance Cgd and that's the point where voltage is dropping somewhat linearly over the mosfet. So it's important to use the 2 volt threshold for the calculation, (or whatever the rated minimum Vth is) because full current will be flowing long before the plateau level is reached.
Most welcome!
As I understand it yeah the miller plateau is the region where the mosfet is working in a linear state so it's easy to see it as being Vth as that's when voltage starts dropping over the mosfet. However they always say 2 to 4 volts for Vth, and the plateau voltage level is always higher, up around 5 ~ 7 volts.
According to the app notes I've read Vth occurs as soon as Cgs is charging, at which point the drain current starts to flow and increases more as Cgs is charged more. Once Cgs is fully charged, it starts charging the miller capacitance Cgd and that's the point where voltage is dropping somewhat linearly over the mosfet. So it's important to use the 2 volt threshold for the calculation, (or whatever the rated minimum Vth is) because full current will be flowing long before the plateau level is reached.
I like your way of looking at it. I know that I tend to oversimplify things, but my impression is that the input capacitance begins to charge from 0 like a simple capacitor until it reaches Vth. Then the conduction begins which removes some charge as the drain voltage decreases, causing the gate to need a higher rate of input current to maintain the same rate of voltage increase. So I would tend to consider the Miller effct to begin at Vth, yet the Miller plateau, with which I am unfamiliar, may be thought of as happening at say 6-8V and not officially beginning as low as Vth.
ummmmm......I think I can agree with that. I was just trying to describe how the plateau portion of the miller effect is much higher than Vth. It gets a little confusing when dealing with so many effects and rates of change and counter effects and.....siiiiiiiiigh. Btw, I have a real tendency to overcomplicate things, a clear sign of a struggle to achieve a deeper, intuitive understanding, which will hopefully allow me to keep things simple, does that make sense?
I will copy and paste a diagram + walk through from t0 to t4 or whatever, which I think will sound exactly as you just described. It's all going to be from a mosfet basics app note from IR I think it's just called "mosfet basics". It's think it's easier to gain a good understanding when you can look at the picture at the same time. I think it's an especially good diagram because it shows drain current versus drain-source voltage versus gate charge. Comming soon!
I will copy and paste a diagram + walk through from t0 to t4 or whatever, which I think will sound exactly as you just described. It's all going to be from a mosfet basics app note from IR I think it's just called "mosfet basics". It's think it's easier to gain a good understanding when you can look at the picture at the same time. I think it's an especially good diagram because it shows drain current versus drain-source voltage versus gate charge. Comming soon!
🙂 I picked up most of my knowledge about mosfet gate drive from IR's Web-site and from just plain ole experimenting.
It sure does.
It sure does.
Alrighty, I decided to forgoe the walk through because that only confuses the matter while the picture is descriptive enough.
Regarding the app notes, some are great! While others, I came across one the other day that, even overlooking the poor grammar, sentence structure, half typed words, "thingsli ke" < that....even some of the graphs were imposed over others..according to some who know alot more than I ever will, the info in them isn't always on the money either. (Fairchild seems famous for these). Still the best resource we have, with that in mind, I should say the equation I brought here regarding gate charge ratio's is right out of fairchilds app notes, I hope it's one they got right!! But it seems to make alot of sense.
Regarding the app notes, some are great! While others, I came across one the other day that, even overlooking the poor grammar, sentence structure, half typed words, "thingsli ke" < that....even some of the graphs were imposed over others..according to some who know alot more than I ever will, the info in them isn't always on the money either. (Fairchild seems famous for these). Still the best resource we have, with that in mind, I should say the equation I brought here regarding gate charge ratio's is right out of fairchilds app notes, I hope it's one they got right!! But it seems to make alot of sense.
This is a bit off topic but..I dont' want to start another thread for such a silly question.
I'm making up the psu for my prototype ucd.
I have a 115V/24V centertap which is rated at 48VA.
Will use a full bridge rectifier, probably 1n4007's. I figured about +-16volt rails? I was just going to slap on some 63V 470uF electrolytics because that's what I have, didn't bother calculating ripple. I'm not going to regulate either. Is that enough? and what kind of power do you think I can get from that.
Oh yeah! I was thinking of making it up on a prototyping pcb I got from radio shack, do you think the traces on it will handle the current ok or should I make it p2p?
Thanks
I'm making up the psu for my prototype ucd.
I have a 115V/24V centertap which is rated at 48VA.
Will use a full bridge rectifier, probably 1n4007's. I figured about +-16volt rails? I was just going to slap on some 63V 470uF electrolytics because that's what I have, didn't bother calculating ripple. I'm not going to regulate either. Is that enough? and what kind of power do you think I can get from that.
Oh yeah! I was thinking of making it up on a prototyping pcb I got from radio shack, do you think the traces on it will handle the current ok or should I make it p2p?
Thanks
With +/-16 volt rails, I figure you may be able to get out something like 10W in 8 ohm before the amp. plays out to the rail, considering that 470uF is a wee bit small for the current delivered to the load at that level.classd4sure said:
If you're not going to exceed +/-30V (or thereabouts), I'm sure a standard prototyping PCB can handle the currents involved.
Regards / Johan.
Hey Johan,
Thanks for that. I found an equation I'm not happy with it's giving me crazy results, for trying to calculate the ripple voltage. I had decided that wasn't enough capacitance so I raided a few PC PSU's for their caps...for 1 270uF per rail. Seems I have to go with p2p because none of the leads of any of the parts fit into the board holes!
Do you think this is enough capacitance now? I have some huge caps in a dead amp I can raid.....seems foolish for such low voltage/power though....I'm not sure.
Thanks for that. I found an equation I'm not happy with it's giving me crazy results, for trying to calculate the ripple voltage. I had decided that wasn't enough capacitance so I raided a few PC PSU's for their caps...for 1 270uF per rail. Seems I have to go with p2p because none of the leads of any of the parts fit into the board holes!
Do you think this is enough capacitance now? I have some huge caps in a dead amp I can raid.....seems foolish for such low voltage/power though....I'm not sure.
I have updated my prototype circuit, as shown in the attached schematic, with some of the details that has been brought up that last few days;
There's suitably calculated reistors from the supply rails to the inverting input, to raise PSRR.
I have also included a buffering OP on the input - a large part of my problems with DC offset was due to the fact that I tried to connect the source directly to the comparator input via a capacitor - there was no way for Q3 to get its bias current that way.
With the OP, that problem goes away. I also took the opportunity to decrease the UcD loop gain (to lower THD), and compensated by amplifying by a factor of 2 with the OP instead.
Finally, I added the pot. that Bruno suggested in the comparator to adjust DC offset.
Unfortunately, the schematic is (for the moment) not possible to simulate in PSpice - I couldn't find a potentiometer with three terminals, so I picked one with two and drew a line to the middle of it to illustrate how things are connected...
Cheers / Johan
There's suitably calculated reistors from the supply rails to the inverting input, to raise PSRR.
I have also included a buffering OP on the input - a large part of my problems with DC offset was due to the fact that I tried to connect the source directly to the comparator input via a capacitor - there was no way for Q3 to get its bias current that way.
With the OP, that problem goes away. I also took the opportunity to decrease the UcD loop gain (to lower THD), and compensated by amplifying by a factor of 2 with the OP instead.
Finally, I added the pot. that Bruno suggested in the comparator to adjust DC offset.
Unfortunately, the schematic is (for the moment) not possible to simulate in PSpice - I couldn't find a potentiometer with three terminals, so I picked one with two and drew a line to the middle of it to illustrate how things are connected...
That's more like it - try it and see 🙂classd4sure said:
Cheers / Johan
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