I figured there are two options to generate the op-amp rails (+/-7V):
1) Generate +/-7V out of SMPS.
2) Generate +/-9V out of SMPS and use LDOs to reduce to +/-7V.
I went for the first one just because there are less components and board space is an issue. One thing working to my advantage is that the SMPS is quite separate from the ADC circuit (with the exception of GND, which we already discussed).
The current design has two separate power "branches":
Pi's 5V -> Pi 3.3V regulator -> SMPS (+/-7V) -> LC filter -> op-amps
Pi's 5V -> ferrite bead -> ESS regulator (3.3V) -> ADC
Components I selected around SMPS theoretically give ripple voltage of <50mV (according to formulas in SMPS datasheet). NE5532 PSRR is specified as 100dB but data sheet doesn't have a plot showing how this rolls off with frequency - OPA161x rolls off at 20dB per decade starting at 10Hz. SMPS operates at 2.1MHz so that is why I was considering LC filter to clean up high frequency noise which the op-amp does not reject at all. I figured 2kHz was reasonable for a cutoff without requiring large components - 47uH with 500mA current rating is available in 3x3mm size. I am going to allow for these on the board and I can test to see if they make any difference.
I am still thinking about the overvoltage question. A power monitor chip might be useful if I can also use it to ensure the startup/shutdown sequence of ADC power rails happens correctly (datasheet says that AVDD needs to be on before AVCC but reference circuit just ties them together). I need to read the TPS3702 datasheet to understand if it can also do this.
1) Generate +/-7V out of SMPS.
2) Generate +/-9V out of SMPS and use LDOs to reduce to +/-7V.
I went for the first one just because there are less components and board space is an issue. One thing working to my advantage is that the SMPS is quite separate from the ADC circuit (with the exception of GND, which we already discussed).
The current design has two separate power "branches":
Pi's 5V -> Pi 3.3V regulator -> SMPS (+/-7V) -> LC filter -> op-amps
Pi's 5V -> ferrite bead -> ESS regulator (3.3V) -> ADC
Components I selected around SMPS theoretically give ripple voltage of <50mV (according to formulas in SMPS datasheet). NE5532 PSRR is specified as 100dB but data sheet doesn't have a plot showing how this rolls off with frequency - OPA161x rolls off at 20dB per decade starting at 10Hz. SMPS operates at 2.1MHz so that is why I was considering LC filter to clean up high frequency noise which the op-amp does not reject at all. I figured 2kHz was reasonable for a cutoff without requiring large components - 47uH with 500mA current rating is available in 3x3mm size. I am going to allow for these on the board and I can test to see if they make any difference.
I am still thinking about the overvoltage question. A power monitor chip might be useful if I can also use it to ensure the startup/shutdown sequence of ADC power rails happens correctly (datasheet says that AVDD needs to be on before AVCC but reference circuit just ties them together). I need to read the TPS3702 datasheet to understand if it can also do this.
Still think you should include patch pads so you can run all power, including +-7v and +5v (otherwise from RPi) all on clean power. RPi power is reputed to be dirty, which should not be too surprising given what it is. Maybe you will get lucky and find your existing power plan is fine. But what if its not?
What would the backup plan be if RPi and or SMPS power turn out to be too dirty? Maybe worth thinking about leaving room for more regulators, maybe even layout some regulator pads that you don't have to populate now? That might save the cost of one board iteration.
What if RPI ground turns out to be too dirty (say, like maybe like when you plug in a grounded analog signal source to digitize)? In a worse case than we talked about so far, maybe consider a two board solution with a shielding, isolation, and or power conditioning hat sitting between RPi and ADC boards?
What would the backup plan be if RPi and or SMPS power turn out to be too dirty? Maybe worth thinking about leaving room for more regulators, maybe even layout some regulator pads that you don't have to populate now? That might save the cost of one board iteration.
What if RPI ground turns out to be too dirty (say, like maybe like when you plug in a grounded analog signal source to digitize)? In a worse case than we talked about so far, maybe consider a two board solution with a shielding, isolation, and or power conditioning hat sitting between RPi and ADC boards?
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Yes I mentioned in a previous comment that I will make sure I can run from outside power supply as you suggested.
Regarding over-voltage - diodes are OK for the inputs, but they will trigger at 3.8V and could bring the VDD rail up. The maximum tolerable VDD is +3.6V, so one solution could be a 3V6 Zener diode on VDD (this is shown in the links in post #95).
Another possibility is to use a power monitor chip to check for overvoltage, but the ones with this feature are $5 compared to <$1 for one with just under-voltage.
Yet another possibility is to use a undervoltage power monitor to monitor the op-amp supply and keep the 3.3V regulator disabled for some time (say 200ms) on startup. That way, the op-amp output voltage in the first 200ms will be clamped to 0V rails on both positive and negative sides. If this approach is feasible, it's probably the best one.
Regarding over-voltage - diodes are OK for the inputs, but they will trigger at 3.8V and could bring the VDD rail up. The maximum tolerable VDD is +3.6V, so one solution could be a 3V6 Zener diode on VDD (this is shown in the links in post #95).
Another possibility is to use a power monitor chip to check for overvoltage, but the ones with this feature are $5 compared to <$1 for one with just under-voltage.
Yet another possibility is to use a undervoltage power monitor to monitor the op-amp supply and keep the 3.3V regulator disabled for some time (say 200ms) on startup. That way, the op-amp output voltage in the first 200ms will be clamped to 0V rails on both positive and negative sides. If this approach is feasible, it's probably the best one.
OK so after deciding to use a power monitor to keep the LDO disabled for a while at startup, and two 1/2W Zener diodes to restrict the 3.3V rail from getting too high, and then struggling for a while longer with finding a decent layout, I have taken a step back and decided that getting this level of performance from an unshielded board in the Pi HAT form factor is at best ambitious, and at worst unrealistic. It is never easy to abandon an idea and change direction, but it will save wasting more time.
I have decided to investigate chips with single-ended inputs to reduce the component count and avoid requiring an SMPS to generate op-amp supply rails, so I am looking at the following:
1. PCM1863. Chip used in HiFiBerry DAC+ADC board. THD+N = -87dB with -1dBFS SE input signal. ~$10AUD. Only requires 3.3V supply. Programmable gain.
2. WM8782. THD+N = -92dB with -1dBFS SE input signal. ~$9AUD. Requires 5V, 3.3V supplies. Built-in op-amps with external resistors to set gain.
3. CS5341. THD+N = -98dB with -1dBFS SE input signal. ~$20AUD. Requires 5V, 3.3V supplies and 1 dual op-amp in single-supply mode on front-end to filter RF noise.
As far as software control, the first two have drivers in the Linux kernel and the third one does not have any SPI/I2C interface - sampling rate would be controlled by jumper and a generic I2S driver would be used.
I am currently planning to go down the CS5341 road - the HiFiBerry board costs over $100AUD to buy here, and I like the idea of creating an option with significantly better performance for quite a bit cheaper. The main concern will be power supply noise but I should have room for some decent-size caps & inductors for filtering.
Once I have a first iteration of the design I will start a new thread. If anyone has any comments or guidance then they are welcome. Thanks everyone for all the help so far - even though it didn't go anywhere yet, I have learned a lot.
I have decided to investigate chips with single-ended inputs to reduce the component count and avoid requiring an SMPS to generate op-amp supply rails, so I am looking at the following:
1. PCM1863. Chip used in HiFiBerry DAC+ADC board. THD+N = -87dB with -1dBFS SE input signal. ~$10AUD. Only requires 3.3V supply. Programmable gain.
2. WM8782. THD+N = -92dB with -1dBFS SE input signal. ~$9AUD. Requires 5V, 3.3V supplies. Built-in op-amps with external resistors to set gain.
3. CS5341. THD+N = -98dB with -1dBFS SE input signal. ~$20AUD. Requires 5V, 3.3V supplies and 1 dual op-amp in single-supply mode on front-end to filter RF noise.
As far as software control, the first two have drivers in the Linux kernel and the third one does not have any SPI/I2C interface - sampling rate would be controlled by jumper and a generic I2S driver would be used.
I am currently planning to go down the CS5341 road - the HiFiBerry board costs over $100AUD to buy here, and I like the idea of creating an option with significantly better performance for quite a bit cheaper. The main concern will be power supply noise but I should have room for some decent-size caps & inductors for filtering.
Once I have a first iteration of the design I will start a new thread. If anyone has any comments or guidance then they are welcome. Thanks everyone for all the help so far - even though it didn't go anywhere yet, I have learned a lot.