And this is the more evolved, 154dB@100Hz variant. Some work will be necessary on the two compensation capacitors. Note that not all the protection components have to be present in all situations; depending on the context, some might be dispensed with (and it applies to the two variants), but as drawn they should be reasonably bullet-proof.
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A looking at stability, switching V1 to DC 420V and hanging an AC1 current, I1 on the output (with 25mA DC load). This graph is from 10kHz to 10MHz. Looks pretty stable to me. (This is the non-invasive analysis method from Omicron-Lab, https://www.omicron-lab.com/applica...tional-and-non-invasive-stability-measurement )
The impedance troughs around 10 microOhms at ~100Hz which is impressive.
The impedance troughs around 10 microOhms at ~100Hz which is impressive.
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Or a CCS (JFET) in the place of the resistor R5. [I did that with following Darlington. Initially also intended as slow-start-up...] - I'm late to the party I see. I was asleep for a long time. Really.Why no Zener diode at the base of Q1? It will increase mains ripple rejection ("PSRR at low frequencies") by many decibels.
Am I wrong or there's a slight displacement to the left and up, to the impedance curve in LTSpice after these changes are made to the original Diego's regulator? Psrr is not affected, and noise we can't get reliable results of.I have used a Dienoiser in the sensitive section of a frequency synthesizer, and I noticed that for 6V the values from the table published by Diego are not optimal.
This is the modified circuit:
View attachment 1295143
With the original values, the the Vce of Q1 was <1V, which is not very healthy: the transistor works in quasi-saturation mode, and the possible correction amplitude is limited.
With R3 at 470 ohm instead of 1K2 and R5 connected differently, the collector voltage is more reasonable, and the current through Q1 is higher, which is beneficial for the noise performance
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