Current feedback amplifier topologies and considerations

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I wand to design a headphone amplifier based on CFA topology (for some very personal aesthetic reason). There are two basic topologies of its input stage which is technically an V-I amplifier (I-V converter providing voltage gain is usually implemented via two current mirrors "fighting" each other). I want to know why one can be preferred to another. In both cases the design procedure is unclear for me. In particular how to choose resistors' values? I have some clues, but I'm not completely sure.

In case a) R1 and R2, I guess, provide some additional Vce room for Q3 and Q4.

Case b) should work well (and it does on simulation) without resistors at all. So, I guess, R3 and R4 may help to minimize some differences in Q5 and Q6 characteristics. But I have no clue how exactly. In case of non zero R3 and R4, R5 and R6 may serve for biasing purposes.

Unfortunately I can't find any article which can explain the procedure. Can you point me to some?

5YLjlKG.png
 
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You can use emitter resistor for Q3 and 4 in version a) too. I'm using the version a) in my power amplifier, and it sounds very well.
The version a) reduce the dissipation, and internal capacitance change in the input pair, which is not in the feedback loop.

Sajti
 
I wand to design a headphone amplifier based on CFA topology (for some very personal aesthetic reason). There are two basic topologies of its input stage which is technically an V-I amplifier (I-V converter providing voltage gain is usually implemented via two current mirrors "fighting" each other). I want to know why one can be preferred to another. In both cases the design procedure is unclear for me. In particular how to choose resistors' values? I have some clues, but I'm not completely sure.

In case a) R1 and R2, I guess, provide some additional Vce room for Q3 and Q4.

Case b) should work well (and it does on simulation) without resistors at all. So, I guess, R3 and R4 may help to minimize some differences in Q5 and Q6 characteristics. But I have no clue how exactly. In case of non zero R3 and R4, R5 and R6 may serve for biasing purposes.

Unfortunately I can't find any article which can explain the procedure. Can you point me to some?

5YLjlKG.png

There is third topology of input stage, look here. http://www.diyaudio.com/forums/soli...pre-phone-amp-low-distortion.html#post4826429
 

PRR

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> should work well (and it does on simulation) without resistors ... may help to minimize some differences in Q5 and Q6 characteristics

Bingo. In SPICE, "same" transistors are *exactly matched*. Exact-same Vbe at a given Ie.

Since you rely on SPICE, you might not know basics. Shockley's Law says (indirectly) that a 20mV difference of Vbe forces a 2:1 difference in Ie; 60mV makes 10:1 difference. So VERY small differences in Vbe make LARGE difference in current.

And in actual production, Vbe varies with mask slop and with baking time.

In real life, I was taught to assume transistors from the same crate could vary 0.1V either way. So a fixed Vbe could give 1mA, 40mA, or 0.025mA.

For "good consistency" from one build to another, I would pick Re to drop 1.0V at desired current. Then the variation might be 0.9mA to 1.1mA, which is usually acceptable.

I have observed, in real life, not counting junk-pack parts (50 for $2), that Vbe varies much less than 0.1V. 0.1V drop in Re is usually good enough. Lately parts on tape are so consistent that <10mV variation is likely, and 9 of 10 builds will be spot-on with less than 0.1V drop in Re.

The cost of the resistors is small. Ask yourself if it hurts to allow 10mV-100mV in each resistor. It will make the scheme MUCH more consistent build to build. (Even if you don't plan a million, you clearly plan two of these.)
 
> should work well (and it does on simulation) without resistors ... may help to minimize some differences in Q5 and Q6 characteristics

Bingo. In SPICE, "same" transistors are *exactly matched*. Exact-same Vbe at a given Ie.

Since you rely on SPICE, you might not know basics. Shockley's Law says (indirectly) that a 20mV difference of Vbe forces a 2:1 difference in Ie; 60mV makes 10:1 difference. So VERY small differences in Vbe make LARGE difference in current.

And in actual production, Vbe varies with mask slop and with baking time.

In real life, I was taught to assume transistors from the same crate could vary 0.1V either way. So a fixed Vbe could give 1mA, 40mA, or 0.025mA.

For "good consistency" from one build to another, I would pick Re to drop 1.0V at desired current. Then the variation might be 0.9mA to 1.1mA, which is usually acceptable.

I have observed, in real life, not counting junk-pack parts (50 for $2), that Vbe varies much less than 0.1V. 0.1V drop in Re is usually good enough. Lately parts on tape are so consistent that <10mV variation is likely, and 9 of 10 builds will be spot-on with less than 0.1V drop in Re.

The cost of the resistors is small. Ask yourself if it hurts to allow 10mV-100mV in each resistor. It will make the scheme MUCH more consistent build to build. (Even if you don't plan a million, you clearly plan two of these.)

But how can emitter resistor help? In case of V-I conversion in just lowers resulting transconductance proportionally. For example emitter degeneration in current mirrors doesn't work this way. It helps to minimize the Early effect on already matched pair. Anyway PNP and NPN transistors have different Vbe and Early voltage even in SPICE.
 
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I like to guesstimate the deltaVbe that might be encountered between two transistors that I hope are "matched". Then I size the emitter degeneration resistors such that (25 x deltaVbe) is dropped across each emitter resistor. This reduces mismatch by roughly a factor of 25.
 
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Originally on my sx and nx-Amplifiers, I had the value of R3,4,5,6 in the second diagram above set to 15 Ohms. There were a number of builder who ran into problems - could not dial the offset out, big current imbalances etc. I raised the resistor values to 150 ohms resulting in a drop of 150mV across each resistor and that solved all of the problems. I have stuck with these values and the 1mS standing current in all my subsequent designs and continue to have success.

I used BC857 and 847 - the worst cased dVbe I've measured is 10 mV but in most cases the average is 3-5mV at 1mA standing current.
 
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Approx. 1mA. Hfe matched to 1%

Sajti

About 30 sx/nx modules were built and the problem came up in about 4 of the modules. After the change (15 Ohms to 150 ohms) there were no more problems and the offset adjustment range was enough to dial out the offset/imbalance.

If you have not had the problem and you are using a standard CFA buffer<>level shifter diamond front end you are a lucky guy. The problem will come up once you have built enough units. If you do not want to change the resistor values, you will need to make sure the Vbe's of the diamond buffer devices are closely matched.

Vbe is the important parameter for this problem BTW -not Hfe.
 
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I did some test in the simulator. Just replace one input bjt to totally different type (2N5401, BC327, BC556 etc.). The worst case was 25% bias change in the input, and VAS, and 77mV offset at the output.

Sajti

I tried that as well - unfortunately it does not cover the spread you get in real life.

Its important to keep this in perspective. If you are only going to build a few units then by all means use low values like 15 Ohms for the degen resistors. If you have the problem - then select the devices. One other trick is to use devices (1 x NPN and 1 x PNP) with the HIGHER Vbe for the input buffer and the ones with the LOWER Vbe for the level shifter function. This almost always guarantees you will not have the problem described earlier.

In my case, since it was a DIY amp getting built by many people, that was not really an option. I think over 100 sets have been sold now (nx V1 and V2 + sx) so that's around 200 channels.
 
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