The filters in the DAMs are full-range. I have not tried to load speaker driver specific band-limited ones yet.
Well, at least it's not too hard to wire them up and play some music, how can you resist?
The Si570 is powered by a standard linear regulator followed by a LC filter, but as per datasheet it is also regulated internally so it's not critical.
Thanks for the information. But where does it say in the datasheet that SI570 has an internal regulator? The only vaguely relevant statement I can find is "DSPLL clock synthesis provides superior supply noise rejection". SI514 datasheet on the other hand clearly states it has built-in LDO.
In my experience using it as MCLK with Ians reclocker, the SI570 is quite sensitive to power supply quality. By "quite sensitive" I mean there seemed to be noticeable differences in sound even with presumably insignificant changes in power supply implementation.
Ok, the Si570 datasheet isn't that detailed and don't say anything directly, but as it is available in both 1.8V / 2.5V and 3.3V versions indicates there is an internal regulator, like in the Si514.
I'm happy with my powering, the linear regulator to take care of low frequency noise and the inductor coupled with several different ceramics to take care of high frequency noise.
Anyway, I don't even believe a Si570 make much difference as the R-2R network is less sensitive to jitter compared to most Delta Sigma converters....
That is certainly true.
As for the insensitivity of SI570 to power supply, I'd say that question is still open for experimental confirmation.
The test board schematic you have published uses an external SI570. Can the onboard SI570 in 1121-01 be used to drive the slave directly?
On a related note, how are the clk lines terminated in 1121-01, especially in slave configuration? Thinking along these lines: Terminating Differential Transmission Lines to Min... - Silicon Labs Community
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Yes, but you need the LVDS buffer. Firmware will autodetect oscillators and only enable one.
Terminated Transmission line with very short stubs, that's why the LVDS buffer....
If it is terminated within the DAC, and the CLK+/CLK- pins are stubs, then the offboard buffer will end up unterminated at its inputs?
In that case it could really be better to use an offboard clock with a fanout buffer.
Or it could also not make any noticeable difference
If it is terminated within the DAC, and the CLK+/CLK- pins are stubs, then the offboard buffer will end up unterminated at its inputs?
In that case it could really be better to use an offboard clock with a fanout buffer.
Or it could also not make any noticeable difference
If you look at a dam1121 board you will notice the onboard oscillator just next to the connector, the internal termination is at the other end, at the LVDS to CMOS translater chip. The external buffer is supposed to also be located just next to the connector, then the stub is very short....
If using more than two boards then a fanout buffer is needed, actually, when using more than two boards it's best with an external oscillator and fanout buffer.
Søren - do you have a preference or recommendation for an IC switch if using multiple SPDIF inputs?
Also, in the 1121 schematic, I assume the M1 and M2 shown above the boards refer to Master 1 (Bal-Left) and Master 2 (Bal-Right) strap configurations for a balanced, non-external clock implementation as against the schematic's external clock configuration? i.e, shouldn't that be labeled S1 and S2 if setting up an external clock? Guess you were covering all bases....😊
Specifically then, if configuring for a balanced unit using onboard clocking, then both 1121s would be strapped as masters and then further strapped as bal-left or bal-right, correct?
And finally, if the above paragraph is indeed correct and both boards are to be strapped as masters then:
a) the En_Aud is an Output and can be left unconnected on both boards- or used via a uC to mute etc?
b) does the I2S output from the isolator have to go first to M1 then from there to M2 or can it go from the isolator to both boards??
Also, in the 1121 schematic, I assume the M1 and M2 shown above the boards refer to Master 1 (Bal-Left) and Master 2 (Bal-Right) strap configurations for a balanced, non-external clock implementation as against the schematic's external clock configuration? i.e, shouldn't that be labeled S1 and S2 if setting up an external clock? Guess you were covering all bases....😊
Specifically then, if configuring for a balanced unit using onboard clocking, then both 1121s would be strapped as masters and then further strapped as bal-left or bal-right, correct?
And finally, if the above paragraph is indeed correct and both boards are to be strapped as masters then:
a) the En_Aud is an Output and can be left unconnected on both boards- or used via a uC to mute etc?
b) does the I2S output from the isolator have to go first to M1 then from there to M2 or can it go from the isolator to both boards??
Any digital mux fast enough can be used, not that critical, can t.ex. be 74VHC or 74LVC logic.
Nothing to do with master or slave, just labeling in schematics....
Clocking is autodetect, if external clock is detected then both master and slave will use it, if no external clock then the master output its internal clock to the slave. When using external clock there can only be one master.
There can be only one master if synchronous clocking. If clocking asynchronous then it's just like multiple dam1021's....
a) EN_AUD is open collector output with internal pullup when master, multiple boards can be connector together.
b) All high speed signals should be routed observing high speed design rules. The easiest is from source terminated source to M1 to M2, with short stubs if needed.
If clocking synchronous then I2S and SPDIF source only goes to input on master module, with input on slave coming from master output, like in example schematics.
Please read the dam1121 manual carefully. The example schematics is for balanced mode with synchronous clocking.
Dear Søren,
Can I direct use Si570 instead of a Si514 to 1121-02 ?
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Schmike
Yes.
The dam1121-01 already have Si570, so you would probably use internal clocks with the -01.
soren im currently using an optical source from PC to the DAM so if we are using a USB receiver like XMOS then I agree that using it with dam 1021 has got galvanic isolators but how about the 1121?
In general for 1021 which one will sound better the USB > XMOS > dam 1021 or using an optical source from a Asus soundcard from PC?
What if USB is used for the DAM1121 as i think there are no galvanic isolators.
In general for 1021 which one will sound better the USB > XMOS > dam 1021 or using an optical source from a Asus soundcard from PC?
What if USB is used for the DAM1121 as i think there are no galvanic isolators.
Please just look a the example schematics in the manual available on www.soekris.dk....
As the dam1021/dam1121 reclocks all inputs then they will sound the same, assuming no bit errors in digital inputs....
soren its not about that reclocking its about the galvanic isolation so both i2s and Optical input goes through galvanic isolators?
I have a scenario to connect it to Raspberry pi but Pi i2s. Its said Pi doesnt have clean power supply or high quality regulators and hence the noise is passed to i2s as well.
At the same time the USB also passes noise to the later stages so i just had a doubt regarding the galvanic isolation being universal to the dam inputs?
A doubt regarding the 1121. As it has following power supplies
+V5D+ for Digital I assume the limit is about 5V or may be 5.2V max
+V5A+
-V5A-
Is for analog section especially for the ladder power supply.
I think the ladder is being powered by and opamp so what is the max power supply for the opamp? or I have a situation that my discrete regulator cannot go less than +/-6.5V
I agree the supply for digital cannot exceed may be 5.2V but the analog supply might be less than 7V?
+V5D+ for Digital I assume the limit is about 5V or may be 5.2V max
+V5A+
-V5A-
Is for analog section especially for the ladder power supply.
I think the ladder is being powered by and opamp so what is the max power supply for the opamp? or I have a situation that my discrete regulator cannot go less than +/-6.5V
I agree the supply for digital cannot exceed may be 5.2V but the analog supply might be less than 7V?