Remember here some do not listen to music anymore, they just measure ! 😆
Me with all those things and debugs I have not time to hear music anymore btw! 🤣
But i agree with the words, they are not salad and very true,but maybe the last phrase that can contredict the first one : it can be a fact it is very bad and a personal opinion to find it good ! But yes pleasure is what matters at the end. Hifi is cruel (and not because it is the World, blah 😉 ) just because you never know there is a better sound of a material you have until you hear it with better hifi layout !
🙂
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Sure , I made some comparisons with other dacs and this one sound just great not to say "better" , this is it , subjective but it , I remenber John told us about the sonic " superiority" of the passive way , fact is that it gives that little something " more " that change it all
but what ever happens facts only will tell us on this new ( only ? ) way to do it , and I'll be the first to compliment him
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@fabrice63 I did not get one thing: Did you reverse the elcaps when sinking them to -15V instead of AGND? A genuine question.
No , as I said before Thorsen is difficult to follow , and english is not my mother language , tomorrow i will do it right , fact is I am interested in the matter as much as I dont like the way the guy comunicate , this is it ......
I will report
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I will report
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Indeed. Note, I am not debating "wrong" or "right", but hotel the internals of the TDA1541 are designed and what are the consequences of this understanding.
I do note for example that running the DEM system at high frequencies and using RF design with all currents returned to a AGND/DGND ground plane is valid and gives excellent results. It is not a "wrong way".
This system may be improved by optimising the current loops and reducing the RF noise dumped into AGND.
The issue here is that we experience a lot of RF disturbances and it may be better to go the opposite way on DEM, which is to use larger value DEM capacitors. It removes an unnecessary source of RF noise.
Of course, you can connect your capacitors to AGND instead of -15V. The difference will be small, mainly AGND will see less switching noise. This needs active probes and fast scopes, you will not see any difference on an FFT for example, unless you get 90dB+ range to 10MHz.
You clearly misunderstand thd whole of what I wrote.
Something I asked that you omitted to answer, when you, as you claimed, tried the "Fabrice63 mod" to DEM decoupling, did you reverse the polarity of the decoupling capacitors, or did you just connect the + side of all DEM capacitors to -15V instead of AGND, thus operating the capacitors in reverse bias, far greater than the ~ 1.2V allowed?
I made clear that what I am writing about is analysing the TDA1541 internal function and drawing conclusions from this. You are absolutely welcome to ignore everything I write.
Thor
I apologise. English is my third language. My first is German and I fall into the German tdndency for long, concatenated sentences, whereas modern international English expects shorter statements.
My problem is that the short sentences tend to remove qualifications dlfrom statements and make them absolute, where they should be relative.
I will suggest to not try it. Your PCB follows a completely different paradigm than what I set out.
You do not use power and ground planes. I do and comments I make on decoupling presume such are used where we are dealing with high frequencies.
If it works well for you, leave alone.
Then put me on ignore and ignore me. No need to get annoyed or upset. I routinely put people I do not want to read and be prompted into replying on ignore.
Thor
No , I won't ignore you just because we don't like and understand each other , I am able to get over that , facts matter the most for me
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What a drama 😀 ! I find Throsten communicating very well actually, clear, precise, no arrogance. Which cannot be said about all the discutants.
The power supplies grouping is sth I do not understand: why grouping them say +/-5V and -15V or 20V with taps etc. Why not isolate all 3 PS down to the transformel level to break the current loops involving PS and control the couplings between them by quality shunts, close to the chip? That's at leats my strategy.
It is best to consider the precise circuit inside TDA1541 and design something that precisely tracks the TDA1541 temperature and minimises voltage swing.
Ideally the swing is limited to around +/-100mV around the precise DC trigger point. This keeps the input stage in the linear range and should avoid noise on +5V/DGND.
I found in the AMR CD-77 I could limit the swing to around 300mV PP using an ECL Driver and a power supply that altogether did good temperature tracking.
The design by MVAL allows excellent thermal tracking. Schotty and pin diodes with lower voltages than 1N5711 exist. So the current 700mV PP swing could be reduced.
Thor
Capacitors were correct polarity? I think not. Also of course watch capacitor voltage rating.
MSB Capacitors see ~ 7.5V DC and LSB capacitors will see around 11.5V DC.
The level of difference you are showing between the two points as current return suggest to me that something else has been changed.
Thor
Current flows in loops. Understanding where current loops originate and terminate is important.
We usually view things like "ground" and "power supplies" as "ideal". But they are not.
If our current loops have to "cross" non-ideal power supplies on the way that causes error voltages we preferrably do not have and which are best avoided.
I don't disagree, but I do not necessarily see any real benefit to a single isolated 20V supply with Tap's or perhaps 10V (mainly digital) tapped and 15V (mainly DEM & analogue).
It was done similar in the CD-77. I have since moved to the tapped stack, as the most critical analogue loop is +5V to -15V.
Thor
Yeah , what a drama , earth still spinning 🤣
dont forget to try what he told you at post 8723 , I am interrested to see the results
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No, I mean that "Ground" as concept is actually a fictional thing. It doesn't exist.
"Ground" is actually another signal and power line. We draw a ground symbol and ignore the resistance, inductance etc.
I have Chinese FPGA boards on order that output simultaneous mode.
I never tested it particularly, because if IIS is handled right, the noise feed through is low. My main reason is actually to enable 384kHz sample rates.
I see the point of Simultaneous mode with delayed LE. I would suggest that LE should be the narrowest possible pulse and as shifted as far "back" so that LE triggers just before the next data is read.
This maximises the benefit. I don't think any current options offer this.
Thor
My "manual added" planes use 2mil Kapton tape and ~3 mil copper.
So you might have an existing PCB, 2 layer, classic TDA1541. The added AGND and -15V plane below the PCB thus have 2mil gaps to the board traces and to each other.
Above the board (need to unsolder TDA1541 or socket) kapton tape to isolate and copper for the DGND plane.
So now we have a 5 layer PCB in the area of the TDA1541.
This also works great for Vero board.
Thor
My quiestion to Sumotan was : has the pin 5 and pin 14 to see each others in order the DAC works if there is no Vref anymore? Have these two pins not to see a closer reference as possible whatever the level is never exactly the same on a layer, or it doesn't matter anymore (cause no ground concept) ?
Thanks for the layout illustration and tips. Question about mil distance was to F63 as I surmised the layout not to be optimal to try efficiently and went fast with what on hands.
At these close distances, wondered if there could have current spikes or too much current enough to couple with the internal of the TDA1541A ? Or a classic not polarized "vref" plane has as much current ? Or not a problem for both (I mean current spread a little in 3D. I don't know if my questions makes sense as I don't want either to open a vegetables garden 🙂 .)
Thanks for the layout illustration and tips. Question about mil distance was to F63 as I surmised the layout not to be optimal to try efficiently and went fast with what on hands.
At these close distances, wondered if there could have current spikes or too much current enough to couple with the internal of the TDA1541A ? Or a classic not polarized "vref" plane has as much current ? Or not a problem for both (I mean current spread a little in 3D. I don't know if my questions makes sense as I don't want either to open a vegetables garden 🙂 .)
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TDA1541 is to precious now to experiment.
I think yes, a link is needed, because the people at Philips when designing the TDA1541 mixed up a analogue and digital nodes together.
Maybe in my build I'll put a pair of Back to Back 1N5711 between the two, 100R resistor and separate +/-5V and -15V and see what the result is. It might work, if so that would be worth knowing. I bought several sony CD Players from which to steal TDA1541 (not A), I have one scheduleded for experiments.
It worked well enough, but looking at the circuit I do wish they had made it a 32 pin IC, with DGND at pin 1 and +5V at 32 and AGND at pin 16 and -15V at pin 17 and with Aox- and Aox+ pins, so we don't mix audio currents into +5V and can use AGND as main return and audio star ground.
In the decades since designers have tended towards separating them. So these days we get clear separation between analogue supplies and grounds and digital ones as well as pinouts with improved decoupling opportunities. And the "return everything to ground" has also given way to more nuanced approaches.
Thor
TDA1541 is to precious now to experiment : exactly what I wrote to Sumotan and of course I putted myself in the same bag.
That's also my basic understanding, they put two pins outside of the substrate because it is to hard to layout inside the substrate or in order to have a very "quiet" reference on a wide layer. But we know now than around the pin 5 one can find an autobahn of currents as John explained well. I try to follow, not easy ! All has to be seen as analog, the zero to one are not instantenous, no ?! They try to separate it not the current spead to much for noise ? Well I digress.
Well we can use starground method with multilayer traces to tie the pins where it belongs, the problem is where should they met at one point (and your answer is btw : near the standalone PS from witch all is derived the voltages. if I sucess to follow your idea - which is not easy for me) ). I remember John saying the "ground" between the pin 14 and 5 had to be clean (understand not crossed by currents (DEM caps, etc) and then proposed a little star way at pin 5 , but whatever it is autobahn and traffic jam at pin 5 !
That's also my basic understanding, they put two pins outside of the substrate because it is to hard to layout inside the substrate or in order to have a very "quiet" reference on a wide layer. But we know now than around the pin 5 one can find an autobahn of currents as John explained well. I try to follow, not easy ! All has to be seen as analog, the zero to one are not instantenous, no ?! They try to separate it not the current spead to much for noise ? Well I digress.
Well we can use starground method with multilayer traces to tie the pins where it belongs, the problem is where should they met at one point (and your answer is btw : near the standalone PS from witch all is derived the voltages. if I sucess to follow your idea - which is not easy for me) ). I remember John saying the "ground" between the pin 14 and 5 had to be clean (understand not crossed by currents (DEM caps, etc) and then proposed a little star way at pin 5 , but whatever it is autobahn and traffic jam at pin 5 !
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Actually I think we create this massive multi-autobahn crossing at pin 5 by not correctly resolving individual current loops.
My take is that many currents can complete their loops without first passing by pin 5, which would simplify things a lot.
And that what was my original post was about. Simplification of the mess around pin5.
Thor
ah we clairly see it is 3D ! (put the -15 V FDEM return layer near the outside of the TDA body at 5 mil from the top layer near the pins and not below between the pins?) in between pins area w/o copper (no stray capacitance between two sides), just the AoL and AoR in that space (no return trace either but outside that internal area) ?
Not new speaker, had it for a while just never put it to use, made a simple OB just to have a listen. How to Sim Dem, Im on I2S direct with Sdtrans player