Hello all.
There is no question about Johns competence, creativity and his kindness to share his findnings. Amirable qualities.
I agree with Toh on the comments above and earlier.
Feedback is the basis of Control Theory.
Servo control, over "slow" blocks, causes "limitations" in application of corrective signal, as pointed out by Toh.
I won't bore you with the details, just think FB will be effective at low frequencies only.
Personally I experimented with servo control many years ago (i.e. including the speaker into the FB loop).
Not a trivial task to apply corrective FB all the way up to 20 kHz.
Suffice it to say, it sounded wonderful at low frequencies and terrible at mids and highs.
Cheers to all.
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Agreed.
We have yet to reach the potentials of digital playback >:-(
Manufacturers are in it to make money.
Audio quality/enjoyment is non-existant words in their vocabulary.
Cheers
Guys, it is not that difficult to try the plain electro-tos-link principle in your own systems. 😉
Check out John's site! 🙂
Cheers and best wishes of success to you ALL.
M.
Check out John's site! 🙂
Cheers and best wishes of success to you ALL.
M.
Bravo...
Things change, usb is better than yesterday, toslink has improved thanks good research, netwok with buffers and less noisy parts show their nose...cool...
All is not bad...look at ec design , totalDac...
Things change, usb is better than yesterday, toslink has improved thanks good research, netwok with buffers and less noisy parts show their nose...cool...
All is not bad...look at ec design , totalDac...
I agree with John on Class D amps.
There are different topologies, but they all require massive FB to clean up the output.
If you wanna loose your lunch, just take an oscilloscope and look at the output on a class D amp prior to the output filter 😉
They design priorities are not compatible with low power, high-end audiophile amps.
I am sure Bruno Putzey would disagree 😉
OK, back to DACs....
I checked the website of ECDesigns and was happy to see some major updates with new products. In fact, they are all new, from the new interface cable to the feedback controlled speakers. The website indicates that, due to the virus pandemic, the supply is low and you cannot order them via their website. Only those with pre-orders can acquire them.
Has anybody received the new Fractal DAC?
Any comments?
Toh
Has anybody received the new Fractal DAC?
Any comments?
Toh
Hi everyone 🙂
Absolutely fantastic thread! I must admit I went through as much pages as I could, but obviously not all, so pls forgive me if my question has already been discussed:
When balancing, why no one seems to use the old Pedja Rogic's simple logic for I2S splitting into L+-/R+-? Everyone going balanced now uses the I2S-PCM conversion and the sim mode?
A bit of a background - I have a pair of very nice Jensen MC stepup transformers that I planned to use in a passive I/V for paralleled TDA1541. I realized however the trannies won't be happy with the unbalanced DC current. One immediate option is of course sinking 2mA/chip via 2.5k from output to +5V, but balancing looks more sexy. I wanted to avoid for the start (it's my 1st DAC) a complicated logic before the DAC's, keeping the digital domain data manipulation to a minimum and was thinking of Pedja's simple I2S splitter based on HEF4517. My receiver chip is 8414. Any comments? Is it sonically better to simply sink 2mA or use Pedja's splitter and go balanced?
Thanks in advance 🙂
PS Pedja's splitter, sorry could not find the original link I2S ground noise issues & possible resolutions - jkeny - Computer Audio Asylum
Absolutely fantastic thread! I must admit I went through as much pages as I could, but obviously not all, so pls forgive me if my question has already been discussed:
When balancing, why no one seems to use the old Pedja Rogic's simple logic for I2S splitting into L+-/R+-? Everyone going balanced now uses the I2S-PCM conversion and the sim mode?
A bit of a background - I have a pair of very nice Jensen MC stepup transformers that I planned to use in a passive I/V for paralleled TDA1541. I realized however the trannies won't be happy with the unbalanced DC current. One immediate option is of course sinking 2mA/chip via 2.5k from output to +5V, but balancing looks more sexy. I wanted to avoid for the start (it's my 1st DAC) a complicated logic before the DAC's, keeping the digital domain data manipulation to a minimum and was thinking of Pedja's simple I2S splitter based on HEF4517. My receiver chip is 8414. Any comments? Is it sonically better to simply sink 2mA or use Pedja's splitter and go balanced?
Thanks in advance 🙂
PS Pedja's splitter, sorry could not find the original link I2S ground noise issues & possible resolutions - jkeny - Computer Audio Asylum
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It is not just to get a balanced output, that we use I2S to PCM but to take advantage of the SIM mode in the TDA1541. It performs way better in this mode.
Thank you Kolby. I understand that in SIM mode there are less I2S operations and hence less generated noise within the chip. But it's a bit complicated and I'd like to start from sth simpler, hence my questions:
- Is Pedja's I2S splitter still a good solution for balancing? 8414 -> Pedja -> 2x TDA1541
- What is sonically preferable, if anyone compared: A) Parallel TDA1541 with resistors sinking 2mA or B) Balanced with Pedja's split?
Connecting to I2S:
-What is the consensus on I2S series resistors connecting to 5V logic? 1k?
Thanks
Hi,
Balancing refers to the output of the dac chip. I2S and the simultaneous mode to the input. The sim mode is the same thant I2S but the data chanels where Left data and Right Data are multiplexed on a same channel are splitted in two channels. The TDA1541A works with either, look at the datasheet. You just need one dac chip for the sim input mode.
Output : you can do single ended or balanced with two dac chips or one with an OT which merge single end to balanced as do P. Rogic or people whom need it for long distance to the pre/amp.
1) yes still feasible if you find a 8414 chip for the spidf though better chips exist today like the opto toslink option from ECdesign here. P. Rogic if you look at Audial thread use as most some classic X-Moss chip for an USB inputt today and sim mode to feed a single TDA1541A chip. Some designs are diy feasible if you read the thread.
2) if talking about outputt and balalncing vs Single Ended, I prefer, YMMV, a single dac chip than two unpaired as measured Jon. Both single and balanced outputt sound good, some prefer an OT cause it breaks also ground loops that are audible in their system and aslo gives a sort of band pass filter. My preference goes to a direct outputt without DC blocking caps -on a single dac chip. -like a discrete diamond output or a tranconductande opa chip (like the opa861) or the many stages John designed here. Often need a cermet pot to biass the two channels at zero volts.
Hope that helps, you should read it all... many many good advices to understand that chip on the inputt and outputt sides of it here... despite the thread merged to new discrete products and more bits than the 15+1 initial TDA1541A bits.
Balancing refers to the output of the dac chip. I2S and the simultaneous mode to the input. The sim mode is the same thant I2S but the data chanels where Left data and Right Data are multiplexed on a same channel are splitted in two channels. The TDA1541A works with either, look at the datasheet. You just need one dac chip for the sim input mode.
Output : you can do single ended or balanced with two dac chips or one with an OT which merge single end to balanced as do P. Rogic or people whom need it for long distance to the pre/amp.
1) yes still feasible if you find a 8414 chip for the spidf though better chips exist today like the opto toslink option from ECdesign here. P. Rogic if you look at Audial thread use as most some classic X-Moss chip for an USB inputt today and sim mode to feed a single TDA1541A chip. Some designs are diy feasible if you read the thread.
2) if talking about outputt and balalncing vs Single Ended, I prefer, YMMV, a single dac chip than two unpaired as measured Jon. Both single and balanced outputt sound good, some prefer an OT cause it breaks also ground loops that are audible in their system and aslo gives a sort of band pass filter. My preference goes to a direct outputt without DC blocking caps -on a single dac chip. -like a discrete diamond output or a tranconductande opa chip (like the opa861) or the many stages John designed here. Often need a cermet pot to biass the two channels at zero volts.
Hope that helps, you should read it all... many many good advices to understand that chip on the inputt and outputt sides of it here... despite the thread merged to new discrete products and more bits than the 15+1 initial TDA1541A bits.
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Very brave of you to remove the DC blocking cap Diyiggy. This approach would be ok if the input of the preamp or amp has already a DC blocking cap. I do wonder though how things would sound like if input of amp itself does not have a DC blocking cap though. Will it work or does one needs to wait for the Dac to warm up till Dc offset has reach zero before we play music or ?????
Cheers
Cheers
indeed, good inputt. I biass your chip and the two outputt opa861 channels after ten minutes of warm up to 0.2 mV after ten minutes of meditation or yoga to calm down the fingers that old the screwdriver 😀.
And my pre has an inputt cap and if I was using without pre my Chord amp has protections
... anyway prudence with micro DC is welcome with the outputt traffo as well !
And my pre has an inputt cap and if I was using without pre my Chord amp has protections
... anyway prudence with micro DC is welcome with the outputt traffo as well !
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Thanks diyiggy, I digged as much as I could through the thread, finding e.g. the 50Hz DEM. I'm trying (wisely or not the sonic result will show) to keep both input and output as simple as possible. Output is I/V on R to Jensen transformer to DHT stage. I've realized the unbalanced dc current (a newbie to TDA1541...) and trying to understand if simple current sinking +5V or balancing a la Pedja will give better results.
I need SPDIF as the primary use of this DAC will be with CD transports (mostly great vintage designs). I've ordered 8414 from China through a known auction site...let's see what comes.
I need SPDIF as the primary use of this DAC will be with CD transports (mostly great vintage designs). I've ordered 8414 from China through a known auction site...let's see what comes.
Hi phixphi,
This one?
http://usr.audioasylum.com/images/0/3745/I2Sbal_splitter.gif
It outputs I2S and TDA1541A produces high deterministic jitter when running in I2S because the latch signal that determines sample timing has to be derived from WS and BCK while the serial data causes ground-bounce.
With Simultaneous mode we can clock in L and R channels simultaneously, this minimises the duration of data activity during the sample steady state. Wait for ground-bounce to reach zero, then generate a separate latch signal (LE) to latch the outputs. This results in lower on-chip jitter. It is more effective than using just balanced configuration in I2S.
HEF4517 is rather slow, it can cause timing issues with higher sample rates, but for 44.1/16 it should be ok
Just add +2mA for each TDA1541A chip and DC-offset will be fine. Paralleling TDA1541A chips makes more sense as it lowers I/V resistor value for same output voltage. This in turn leads to lower output impedance at the transformer output. You have to multiply I/V resistor value with transformation ratio squared to get approx. output impedance.
33 Ohms I/V resistor and 1:6 transformation ratio results in 1188 Ohms output impedance.
16.5 Ohms I/V resistor (2 x TDA1541A in parallel) and 1:6 transformation ratio results in 594 Ohms output impedance.
8.25 Ohms I/V resistor (4 x TDA1541A in parallel) and 1:6 transformation ratio results in 297 Ohms output impedance.
I personally would try to keep output impedance below 500 Ohms.
Active circuits always add distortion and may easily become unstable (capacitive load) producing even more distortion. I personally try to avoid any active circuit in the signal path that isn't absolutely necessary.
It is best to use a relatively high voltage for bias, 24V for example. This will allow for higher bias resistor value that will then better approximate a CCS.
R = V / I
With +24V and +2mA bias R = 24 / 0.002 = 12K
For two TDA1541A chips in parallel: 24 / 0.004 = 6K
For 4 chips in parallel: 24 / 0.008 = 3K
When a tube anode voltage is present, say +200V it can also be used for bias:
With +200V and +2mA bias R = 200 / 0.002 = 100K. I used this solution in one of my prototypes and probably documented it on this thread.
The higher the bias voltage and related bias resistor value, the better.
You can fine tune the bias resistor value for exactly zero volts DC-offset so there are no problems with the transformer.
I stopped using CCS because of frequency dependent impedance, thermal drift and grainy sound.
It is also possible to connect the I/V resistor to a positive reference voltage that nulls the DC-offset instead of connecting the I/V resistor to ground. This reference voltage depends on the I/V resistor value and total half-scale current of the TDA1541A chip(s).
With 33Ohms I/V resistor and one TDA1541A the positive bias voltage would have to be approx. R * I = 33 * 0.002 = 66mV. You can use a voltage divider of approx. 1K and 13.4 Ohms. Large value electrolytic cap (10,000uF/ 6.3V) can be placed in parallel with 13.4 Ohms this will give a corner frequency of 1.2 Hz.
Keep in mind that DC can still occur on the transformer during power up / power down. Easy solution is a small signal relay that shorts the TDA1541A output to ground (no problem at all because TDA1541A has constant current outputs) using normally closed contacts. The relay receives power when the supplies are within range, then the contacts open and signal can flow.
I tested many S/PDIF receiver chips exhaustively, the best one I found is the DIR9001. It is very easy to implement as well. CS8212, CS8214 and CS8216 have high intrinsic jitter (data sheets) and deterministic jitter (data flow) is even worse. The WM8804 has a fractional divider and outputs highest jitter of all chips we tested. DIX9211 (192 KHz version of the DIR9001) also introduces more jitter and interference compared to the DIR9001 as it requires a micro controller to configure it after power-up.
The DIR9001 requires a loop filter (PLL) this loop filter can be tweaked to obtain better jitter attenuation at the cost of slower locking and limited locking range.
When using a coaxial interface you need an insulation transformer and a suitable differential receiver as the DIR9001 only accepts 3V3 level S/PDIF signal.
Parts required,
1) Insulation transformer:
https://uk.farnell.com/murata-power-solutions/da101c/transformer-1-1-0-01h-0-0206h/dp/1362398
2) 75 Ohm load resistor on the secondary winding.
3) Differential receiver receiver FIN1002:
https://uk.farnell.com/search?st=fin1002
4) 2 x 10K resistor for biasing FIN1002 pin 4 to half the supply voltage, the FIN1002 works fine on 3V3:
Pin 4 -> 10K to 3V3 and PIN 4 -> 10K to GND
The FIN1002 outputs a 3V3 signal that can be fed into the DIR9001.
This one?
http://usr.audioasylum.com/images/0/3745/I2Sbal_splitter.gif
It outputs I2S and TDA1541A produces high deterministic jitter when running in I2S because the latch signal that determines sample timing has to be derived from WS and BCK while the serial data causes ground-bounce.
With Simultaneous mode we can clock in L and R channels simultaneously, this minimises the duration of data activity during the sample steady state. Wait for ground-bounce to reach zero, then generate a separate latch signal (LE) to latch the outputs. This results in lower on-chip jitter. It is more effective than using just balanced configuration in I2S.
HEF4517 is rather slow, it can cause timing issues with higher sample rates, but for 44.1/16 it should be ok
Just add +2mA for each TDA1541A chip and DC-offset will be fine. Paralleling TDA1541A chips makes more sense as it lowers I/V resistor value for same output voltage. This in turn leads to lower output impedance at the transformer output. You have to multiply I/V resistor value with transformation ratio squared to get approx. output impedance.
33 Ohms I/V resistor and 1:6 transformation ratio results in 1188 Ohms output impedance.
16.5 Ohms I/V resistor (2 x TDA1541A in parallel) and 1:6 transformation ratio results in 594 Ohms output impedance.
8.25 Ohms I/V resistor (4 x TDA1541A in parallel) and 1:6 transformation ratio results in 297 Ohms output impedance.
I personally would try to keep output impedance below 500 Ohms.
Active circuits always add distortion and may easily become unstable (capacitive load) producing even more distortion. I personally try to avoid any active circuit in the signal path that isn't absolutely necessary.
It is best to use a relatively high voltage for bias, 24V for example. This will allow for higher bias resistor value that will then better approximate a CCS.
R = V / I
With +24V and +2mA bias R = 24 / 0.002 = 12K
For two TDA1541A chips in parallel: 24 / 0.004 = 6K
For 4 chips in parallel: 24 / 0.008 = 3K
When a tube anode voltage is present, say +200V it can also be used for bias:
With +200V and +2mA bias R = 200 / 0.002 = 100K. I used this solution in one of my prototypes and probably documented it on this thread.
The higher the bias voltage and related bias resistor value, the better.
You can fine tune the bias resistor value for exactly zero volts DC-offset so there are no problems with the transformer.
I stopped using CCS because of frequency dependent impedance, thermal drift and grainy sound.
It is also possible to connect the I/V resistor to a positive reference voltage that nulls the DC-offset instead of connecting the I/V resistor to ground. This reference voltage depends on the I/V resistor value and total half-scale current of the TDA1541A chip(s).
With 33Ohms I/V resistor and one TDA1541A the positive bias voltage would have to be approx. R * I = 33 * 0.002 = 66mV. You can use a voltage divider of approx. 1K and 13.4 Ohms. Large value electrolytic cap (10,000uF/ 6.3V) can be placed in parallel with 13.4 Ohms this will give a corner frequency of 1.2 Hz.
Keep in mind that DC can still occur on the transformer during power up / power down. Easy solution is a small signal relay that shorts the TDA1541A output to ground (no problem at all because TDA1541A has constant current outputs) using normally closed contacts. The relay receives power when the supplies are within range, then the contacts open and signal can flow.
I tested many S/PDIF receiver chips exhaustively, the best one I found is the DIR9001. It is very easy to implement as well. CS8212, CS8214 and CS8216 have high intrinsic jitter (data sheets) and deterministic jitter (data flow) is even worse. The WM8804 has a fractional divider and outputs highest jitter of all chips we tested. DIX9211 (192 KHz version of the DIR9001) also introduces more jitter and interference compared to the DIR9001 as it requires a micro controller to configure it after power-up.
The DIR9001 requires a loop filter (PLL) this loop filter can be tweaked to obtain better jitter attenuation at the cost of slower locking and limited locking range.
When using a coaxial interface you need an insulation transformer and a suitable differential receiver as the DIR9001 only accepts 3V3 level S/PDIF signal.
Parts required,
1) Insulation transformer:
https://uk.farnell.com/murata-power-solutions/da101c/transformer-1-1-0-01h-0-0206h/dp/1362398
2) 75 Ohm load resistor on the secondary winding.
3) Differential receiver receiver FIN1002:
https://uk.farnell.com/search?st=fin1002
4) 2 x 10K resistor for biasing FIN1002 pin 4 to half the supply voltage, the FIN1002 works fine on 3V3:
Pin 4 -> 10K to 3V3 and PIN 4 -> 10K to GND
The FIN1002 outputs a 3V3 signal that can be fed into the DIR9001.
Hi phixphi,
If its okay to ask the value of I/V resistor, the step-up transforsmer ratio, the triode type (number) and how you are loading the tube?
My first thought is 2mADC injection, but if you're not married to the DHT, there are alternative triodes, although not direct heated, which were designed for low signal levels, and low noise applications.
There is an option to avoid the CCS and the transformer altogether, and simply bias an appropriate tube with the current offset (remember its a negative current) of the 1541A through the IV resistor, tube cathode direct to signal common, which probably saves you a couple extra parts from the cathode/filament circuit as well.
You can get from TDA1541A: >2vRMS output at <600 ohms with one transformer, one triode, a single resistor and have 0VDC at the output (no capacitors).
Cheers,
HK
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It would depend on the bias conditions of the input stage and the offset voltage at the output of the OPA861.
And yes, depending on the thermal conditions at where you'd trimmed for 0V (impossible in my experience, settling at +/-20mV was about the best I could find amongst various 1541A samples), for direct connection at the 'closest to 0V' offset, all else being equal, you would need the whole thing to be under the same condition as when it was trimmed 'zero' volt offset.
HK
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Hi Hanze, cool to hear from you in those difficult times.
yes sorry, 20mV not the 0.2 mV I wrote !
@ Sumotan : what if the DC blocking cap was huge enough to proceed an High pass one octave below 20 hz for instance : would our ear still can hear it while it still provide DC blocking protection ? Should Phixphi (what a name 🙂 ) should buy cheap polypro cap like Solen to acheive such a goal and have more linearity than an outputt traffo ? Though I also understand a traffo could provide a pretty HD structure like some tubes...
Btw folk, when people like Thorsten Loesch uses a tube for the I/V and "quiet" D3A tubes or a tube made for communication with low noise construction, would the HD structure : h2,h3,h4,h5... is important in the sounding result for this I/V structure ? I also assume there are micro tubes that should work and less hard to find than a NOS matched D3A pair ?!
@John : thank you for this educated long inputt 🙂 . I read some paper about the aging of ceramic class II caps that are far more fast than I exepected (capacitance, esr, leak?)! Have we still to use it please in our precision dac designs or glue to acrylic caps (like it a lot I must say) when precision is not a concern and ceramic class I when precision is needed ? Or just use derating by choosing higher voltage value than needed in the dac circuity ? Some uses X7R smd because they can get a very low inductance by choosing low sizing case form like 0403 size case, but is it still a good idea after 2 000 hours of working condition ? Or finally would not we care about noise too much like the best tubes designs (music is noise and as far odd harmonics stay lower than the uper H2, H4, H6 one can stay safe and accept anyway the speaker distorse more and that a light coloration does not arm? I strongly think about TotalDac tubes outputs stages despite R2R very precise resistors in its ladder discrete dac construction : paperwritters seems to like it at ears... wel dunno if they are objective though !)
yes sorry, 20mV not the 0.2 mV I wrote !
@ Sumotan : what if the DC blocking cap was huge enough to proceed an High pass one octave below 20 hz for instance : would our ear still can hear it while it still provide DC blocking protection ? Should Phixphi (what a name 🙂 ) should buy cheap polypro cap like Solen to acheive such a goal and have more linearity than an outputt traffo ? Though I also understand a traffo could provide a pretty HD structure like some tubes...
Btw folk, when people like Thorsten Loesch uses a tube for the I/V and "quiet" D3A tubes or a tube made for communication with low noise construction, would the HD structure : h2,h3,h4,h5... is important in the sounding result for this I/V structure ? I also assume there are micro tubes that should work and less hard to find than a NOS matched D3A pair ?!
@John : thank you for this educated long inputt 🙂 . I read some paper about the aging of ceramic class II caps that are far more fast than I exepected (capacitance, esr, leak?)! Have we still to use it please in our precision dac designs or glue to acrylic caps (like it a lot I must say) when precision is not a concern and ceramic class I when precision is needed ? Or just use derating by choosing higher voltage value than needed in the dac circuity ? Some uses X7R smd because they can get a very low inductance by choosing low sizing case form like 0403 size case, but is it still a good idea after 2 000 hours of working condition ? Or finally would not we care about noise too much like the best tubes designs (music is noise and as far odd harmonics stay lower than the uper H2, H4, H6 one can stay safe and accept anyway the speaker distorse more and that a light coloration does not arm? I strongly think about TotalDac tubes outputs stages despite R2R very precise resistors in its ladder discrete dac construction : paperwritters seems to like it at ears... wel dunno if they are objective though !)
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Hi John, thank you so much for your in-depth analysis and the time you spent on it 🙂
Yes, that's the one I meant. Thank you for the clarifications.
Isn't it the case with the balanced operation too? I.e. the I/V R is half the value for a single chip?
The plan is to use either 18R or 25R for 2xTDA1541 (to be determined by ear), then 1:8 transformer (configurable to 1:4), then a DHT stage with amplification about 5.
This is a very cool idea. Not sure if I'm getting it correctly, but what will then close the loop for the 2mA DC? I attach a drawing of how I understood it. As far as I could get how TAD1541 works, the output current loop is between the output pins and the +5V?
As for the CCS, the simplest in nature is a choke 🙂 Have you thought in that direction? Instead of a resistor to use a choke, with its DCR tailored to balance the 2mA and the reactance blocking any HF residuals?
Sounds more complicated than the previous solution, esp. with a cap and a new corner added. Is there any sonic advantage of this solution wrt the previous?
The transformers are setp-ups for a cartridge. It generates some occasional DC at lowering/rising/clicks/pops etc so the tranny should be ok with an occasional DC startup/switch off
I've ardered already 8414 plus created a small board for it. A it is on a separate board, I can try what you describe in a future.
Thank you again John for your kindness!
Yes, that's the one I meant. Thank you for the clarifications.
Isn't it the case with the balanced operation too? I.e. the I/V R is half the value for a single chip?
The plan is to use either 18R or 25R for 2xTDA1541 (to be determined by ear), then 1:8 transformer (configurable to 1:4), then a DHT stage with amplification about 5.
This is a very cool idea. Not sure if I'm getting it correctly, but what will then close the loop for the 2mA DC? I attach a drawing of how I understood it. As far as I could get how TAD1541 works, the output current loop is between the output pins and the +5V?
As for the CCS, the simplest in nature is a choke 🙂 Have you thought in that direction? Instead of a resistor to use a choke, with its DCR tailored to balance the 2mA and the reactance blocking any HF residuals?
Sounds more complicated than the previous solution, esp. with a cap and a new corner added. Is there any sonic advantage of this solution wrt the previous?
The transformers are setp-ups for a cartridge. It generates some occasional DC at lowering/rising/clicks/pops etc so the tranny should be ok with an occasional DC startup/switch off
I've ardered already 8414 plus created a small board for it. A it is on a separate board, I can try what you describe in a future.
Thank you again John for your kindness!