Hi Scott,
Yes. That's why the diamond buffer was in my mind to begin with. There's all kinds of stuff going on in that one.
Shouldn't the gates for J29 and 30 be tied to common?
-Chris
Yes. That's why the diamond buffer was in my mind to begin with. There's all kinds of stuff going on in that one.
Shouldn't the gates for J29 and 30 be tied to common?
-Chris
I know that. I have posted a spectrogram. According to my information, the simulator calculates the distortion accurately, since the level of 0.000,1% or more. You have achieved much more distortion, and the simulator is never wrong for levels of distortion at 0.002%. This is a very good simulator, but you can check out your advice to other simulator. It will show the same.
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They are the stupid graphic fell between pixels, it's the minus input. This is kind of frustrating for me, years ago I spent hours of my own time trying to show how some simple circuits could get dramatic results and I went to the length of actually building them and publishing the results (always placing everything in the public domain).
The truth is, it's not my model. Thanks for them Bob and other people.
DropMeFiles ? free one-click file sharing service
Tell me, is the right model, I could be wrong.
It is beyond me why someone would continue to argue with two or more master electrical engineers who have some 40 years of experience behind them.
But it does seem that someone shows up ever few month to do so.
But it does seem that someone shows up ever few month to do so.
I think it's great, something similar could be done on amps with the LTP+CM type VAS such as the Goldmund (which is the only one I can name).
You do not reach a high level of understanding without disagreeing with the highest authorities at least long enough to see your mistake. Granted, this doesn't have to be a stressful process.
I was still looking at the input mirror biasing
hadn't appreciated the diff pair VAS - I do see the cancellation now that it has been pointed out
I must confess to a bias against dual complementary stages in general given the hype about the symmetry
but in this case it is like devices that you are expecting the cancelling from rather than the N vs P halves
hadn't appreciated the diff pair VAS - I do see the cancellation now that it has been pointed out
I must confess to a bias against dual complementary stages in general given the hype about the symmetry
but in this case it is like devices that you are expecting the cancelling from rather than the N vs P halves
Yes but there is a difference between arguing to gain an understanding and arguing just to be right.
Or simply just arguing to make someone else wrong.
I have no reason to mystify someone and spread the model. 🙂
Maybe we use different models of transistors. Maybe too big the DC component of the output.
Sometimes this offset can also increase distortion.
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It's not offset that causes false .four reports, it is drift. When the simulator solves the operating point correctly, there is no drift.
The .four command doesn't use a very powerful FFT window it seems, so it tends to be influenced more by drift than the FFT window when you use Hann, Blackman or Blackman-nuttal windows.
The .four command doesn't use a very powerful FFT window it seems, so it tends to be influenced more by drift than the FFT window when you use Hann, Blackman or Blackman-nuttal windows.
Hi guys,
Happy new year to start
Can someone help me out with the 2sk134 and 2sj49 mosfet models, so I can complete Bob's DH220C modification.
I post the .asc file here, using a bjt ops, if you are interested.
http://www.diyaudio.com/forums/solid-state/31131-hafler-dh-200-220-mods-134.html#post4932974
I have since added the DC servo and the CFP Vbe multiplier, see attched
Thanks
Rick
Happy new year to start
Can someone help me out with the 2sk134 and 2sj49 mosfet models, so I can complete Bob's DH220C modification.
I post the .asc file here, using a bjt ops, if you are interested.
http://www.diyaudio.com/forums/solid-state/31131-hafler-dh-200-220-mods-134.html#post4932974
I have since added the DC servo and the CFP Vbe multiplier, see attched
Thanks
Rick
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Hi T117,
Nearly everyone here knows that I am a strong advocate of using SPICE simulation, especially with LTspice. Most of the time, LTspice gives you a very accurate result for the models and circuits that you give it. However, models are a constant shortcoming, even when they are created carefully. I have suffered at the hand of bad manufacturer's models and that is why I put a great deal of effort into creating my own. This does not mean that my models are the world's best. I just believe that they are just less inaccurate than the manufacturers' models for the parts I modeled.
SPICE results are inherently limited by the accuracy of the models and by the absence of most real-world parasitics in the schematic.
The greatest value in SPICE simulation is the insight that it gives and the ability to see cause and effect, and to avoid errors, and to enable evaluation of different circuit topologies.
One of the weaker aspects of using SPICE is to evaluate distortion in an absolute sense. I have had SPICE simulations give both higher and lower distortion than the real-world circuit. As an example, when I design a MOSFET power amplifier without MOSFET models that model subthreshold conduction, the simulated distortion may actually be higher than in the real-world circuit. That having been said, it is still extremely valuable in evaluating circuit distortion and the changes in circuit distortion that will result if various circuit changes are made.
Cheers,
Bob
The greatest benefit from this occurs at 1KHz where the majority of distortion does in fact come from the Early effect on Q9. Of course by now all of this is buried in noise and the increasingly impossible job of the prototype designer is nowhere near finished.
-151.9db to -175.8db is a 24db (16x) improvement.
-151.9db to -175.8db is a 24db (16x) improvement.
Attachments
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Hi Rick,
Here are the models that I recommend using. These VDMOS models use the LTspice parameter ksubthres to model sub-threshold conduction. I did the original simulations with ordinary VDMOS models and got sim results worse than my measured real-world results. I was actually in the process of creating these models today so that when I (finally) post the .asc it will simulate with these improved models.
Cheers,
Bob
Hi Scott,
Between app notes and your own work, no one can doubt how hard you work to teach. I get it, and I'm sure many others do too. One good thing about an application note. You only have to argue with your peers. Now with simulators, everyone is an expert.
Thanks from the silent majority who understands at least some of it.
-Chris
That makes a whole lot more sense, thank you. I may not get the entire circuit, but I'm working on understanding it.
Between app notes and your own work, no one can doubt how hard you work to teach. I get it, and I'm sure many others do too. One good thing about an application note. You only have to argue with your peers. Now with simulators, everyone is an expert.
Thanks from the silent majority who understands at least some of it.
-Chris