Here Self discusses thermal design and he bases the sizing of the transistors and heatsinks on the power dissipated with the amp at full power:
The Signal Transfer Company: Thermal Design
However maximum dissipation in the output transistors for a low bias class AB amp is at about 39% of maximum output. See here in Figure 5 where the maximum dissipation is about 40W for a 100W max amp:
http://www.ortodoxism.ro/datasheets/BurrBrown/mXystxx.pdf
Bob, you give 1/3 power in your book, did I miss something that would explain the difference?
The Signal Transfer Company: Thermal Design
However maximum dissipation in the output transistors for a low bias class AB amp is at about 39% of maximum output. See here in Figure 5 where the maximum dissipation is about 40W for a 100W max amp:
http://www.ortodoxism.ro/datasheets/BurrBrown/mXystxx.pdf
Bob, you give 1/3 power in your book, did I miss something that would explain the difference?
the "test at 1/3power" is just that, a standardised test. Many adopt and many more ignore it because it is too onerous for their low quality product.
Bob did not claim that this "test power" level resulted in worst case dissipation for the output stage.
Bob did not claim that this "test power" level resulted in worst case dissipation for the output stage.
Hi Pete,
You didn't miss anything, but I was being a bit inexact in my language in the book. I cited 1/3 power in the text because that is the conventional wisdom that always seems to be stated.
The true peak for a truly ideal amplifier occurs at about 40.5% of maximim output power, assuming the output signal can swing all the way to the rails. For such an ideal amplifier, the power dissipation curve is remarkably flat in the central region. Power dissipation at 1/3 power is only about 1% less than it is at 40.5%. Nevertheless, in Chapter 5, pg. 105 I should have been more clear about the theoretical maximum, perhaps with a paranthetical statement.
Note also that the point of maximum power dissipation in a real amplifier with higher rails for a given maximum power output and with things like emitter resistors will be different, often occurring at a higher percentage of peak power as shown in Figure 5.6.
I appreciate your feedback on this, as this is just the sort of thing I need to help me improve the book on the second printing or on the second edition.
Cheers,
Bob
Hi Pete,
There was of course nothing wrong with Glen's analysis - it was just a matter of what tolerences we chose to work with and what we each defined as "well-balanced circuitry with precision resistors" as described in the text. I should have been more specific about that.
I think it is also true that I was unnecessarily agressive with the input stage gain in the example of Figure 7.10. Going forward, I'll probably double (approximately) the value of the current mirror emitter resistors to 1k and double the value of the VAS emitter resistors to 47 ohms. This keeps the VAS quiescent current at 10 mA while reducing sensitivity to mismatches by a factor of 2. I'll also approximately halve the shunt resistors (R14, 16) to 22k, halving again the sensitivity, for a total reduction in sensitivity by a factor of four.
There is very little "cost" to doing this, since the input stage will still have plenty of DC gain (24 dB) and the VAS has transconductance to burn. Even with a large +/- 10 mV offset, the VAS current will then only vary from 8.4 to 12.2 mA. BTW, the original circuit was built and simulated with 2SC3503/2SA1381 VAS transistors.
Even with these changes, the circuit is still far superior to the conventional approach of just a resistor load on the input stage (which also has its own sensitivity issues), providing about 14 dB more input stage DC gain and enforcing much better balance of collector currents in the input differential pairs.
Cheers,
Bob
Yes, this makes sense. I think the main reason for providing an example that is more tolerant of mismatch is that some people will just try to copy the example as is. Certainly others will understand the tradeoff and select values appropriate for their application. Any example demonstrates the concept but again more will believe it if the example can be easily built and tested.
I first noticed it in Chapter 14 Figure 14.1 and the surrounding text. I think the 1/3 power figure became popular because there was a lot of talk about it being nearly the maximum when the FTC came out with that figure for burn in. I've mentioned 1/3 here as being nearly the maximum because I could not remember the exact figure but I was fairly certain that it was higher and happened to look it up a few months ago. My brother and I discussed this at length, years ago when the FTC ruling came out; he did the math to prove the 40.5% number which I stubbornly did not initally believe because it is unintuitive.
Looking at Chapter 5 and Figure 5.6 I'm wondering did you assume that the 48V supply was ideal (regulated) or is the extra voltage required to cover saturation drop in the output stage or to cover the finite source resistance of an unregulated supply? I suppose it could be both.
While reading Chapter 5 I noticed that R1 in Figure 5.7 b is 15 ohms - it has been traditionally 100 ohms in most quasi-comp designs. 15 ohms skews the bias current in the drivers, obviously.
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Hi Pete,
In Figure 5.6 I assumed a constant voltage for the 48-V supply. It is mainly 48V to cover all of the headroom needed by the VAS, output triple, output transistor voltage drop and emitter voltage drop with some reasonable margin.
The shape of the dissipation curve would probably be a bit different if a real supply with sag was used that sagged to 48V at full power, but which might be sitting at a higher voltage at intermediate power levels.
Fortunately, I cannot take credit for the quasi-complementary output stage of Figure 5.7b. With the exception of the transistor types used, I believe it is straight off the schematic of the old Citation 12.
I really appreciate your thorough reading of the book and the questions and feedback you are providing. This really helps me find errors, things that should be revised, or statements that need to be clarified.
Cheers,
Bob
Thanks Bob,
Here is the Citation 12 factory manual, it is 100 ohms:
http://manuals.harman.com/hk/Service Manual/Citation twelve sm.pdf
It is also 100 ohms in the RCA reference design which I can scan for you if you are interested.
Here is the Citation 12 factory manual, it is 100 ohms:
http://manuals.harman.com/hk/Service Manual/Citation twelve sm.pdf
It is also 100 ohms in the RCA reference design which I can scan for you if you are interested.
Hi Pete,
You are right! My figure appears to contain a blatant error in the value of R1 in Figure 5.7. I think the stage was still taken from the Citation, but I have no idea how that value snuck in there (that section was probably done at least a year and a half ago). Now that I look at it the way I should have this morning, that value for that resistor makes no sense. I apologize for missing that this morning. Thanks again.
Cheers,
Bob
AES in San Francisco
Is anyone here planning on attending the AES convention in San Francisco next week? If so, let me know, and try to see Jan Didden and I in Booth 814.
(McGraw-Hill, Linear Audio and Cordell Audio).
Cheers,
Bob
Is anyone here planning on attending the AES convention in San Francisco next week? If so, let me know, and try to see Jan Didden and I in Booth 814.
(McGraw-Hill, Linear Audio and Cordell Audio).
Cheers,
Bob
Thanks for correcting that, Jan.
Yes, Booth 1814. On the left, against the wall, as you enter the exhibit hall.
Cheers,
Bob
More amazon.co.uk woes -
"We regret to inform you that your order will take longer to fulfill than originally estimated. Our supplier has notified us that there is a delay obtaining stock for the following items you ordered on August 03 2010.
We are awaiting a revised estimate from our supplier, and will email you as soon as we receive this information".
"We regret to inform you that your order will take longer to fulfill than originally estimated. Our supplier has notified us that there is a delay obtaining stock for the following items you ordered on August 03 2010.
We are awaiting a revised estimate from our supplier, and will email you as soon as we receive this information".
Hi Ihan,
I'm sorry to hear this. It is very strange in light of the fact that deliveries have been made in many other parts of the world, including Australia, Japan and Romania.
Sorry,
Bob
Hi Bob,
A few questions came to mind as I read Chapter 3.
I found serious issues with the 21193/94 models years ago - one of them was obviously bad did you use corrected models? I also found issues with the MJE243/253 and am wondering if you corrected these also or found better models.
Here is what I downloaded from OnSemi just a month or so ago and you can see
that the date is 2003, and the BF=10000:
downloaded 9-17-2010
* Model generated on Sep 10, 03
* MODEL FORMAT: PSpice
.MODEL BADMJ21194 npn
+IS=4.02325e-14 BF=10000 NF=1.1488 VAF=10000
+IKF=0.377331 ISE=2.16244e-09 NE=2.49213 BR=0.1
+NR=1.5 VAR=1.70851 IKR=3.77331 ISC=1.00031e-16
+NC=3.99945 RB=0.1 IRB=0.1 RBM=0.1
+RE=0.00775691 RC=0.0387846 XTB=0.1 XTI=1
+EG=1.05 CJE=1.07724e-08 VJE=0.975489 MJE=0.524369
+TF=1e-08 XTF=2.16157e+06 VTF=0.184568 ITF=5.56361
+CJC=2.68609e-10 VJC=1.64862 MJC=0.242322 XCJC=0.1
+FC=0.910137 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
I see you offered a .zip file earlier in the thread and you use the MJL versions
with models identified as: mfg=OnSemi060708
Are these straight from OnSemi or did you modify them?
Just downloaded the MJL models from OnSemi and they are dated 2004:
.MODEL mjl21193 pnp
+IS=2.37302e-11 BF=92.8585 NF=0.85 VAF=1000
+IKF=7.81463 ISE=9.34142e-13 NE=1.83168 BR=1.39987
+NR=0.905395 VAR=421.163 IKR=1.8668 ISC=9.34142e-13
+NC=3.03125 RB=14.6266 IRB=0.1 RBM=0.149902
+RE=0.000682292 RC=0.146081 XTB=1.32633 XTI=1.05623
+EG=1.05 CJE=1.15773e-08 VJE=0.57352 MJE=0.417157
+TF=1e-08 XTF=1.946 VTF=17401.6 ITF=3.36265
+CJC=5e-10 VJC=0.95 MJC=0.23891 XCJC=0.999998
+FC=0.987529 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
* Model generated on Jan 25, 2004
* Model format: SPICE3
.MODEL mjl21194 npn
+IS=9.56205e-11 BF=62.3633 NF=0.858602 VAF=29.6613
+IKF=9.86004 ISE=7.00007e-12 NE=3.43749 BR=4.96358
+NR=0.925054 VAR=6.18692 IKR=4.87016 ISC=3.25e-13
+NC=4 RB=11.0204 IRB=0.1 RBM=0.1
+RE=0.000675706 RC=0.124974 XTB=0.150823 XTI=1.00001
+EG=1.11955 CJE=1.70807e-08 VJE=0.4 MJE=0.520397
+TF=1e-08 XTF=47.3046 VTF=1.88154 ITF=0.560261
+CJC=5e-10 VJC=0.95 MJC=0.238884 XCJC=0.800727
+FC=0.8 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
* Model generated on Jan 25, 2004
* Model format: SPICE3
BTW, if you just add .inc transistors.txt to your sims then there is no need for users
to modify their spice libraries.
A few questions came to mind as I read Chapter 3.
I found serious issues with the 21193/94 models years ago - one of them was obviously bad did you use corrected models? I also found issues with the MJE243/253 and am wondering if you corrected these also or found better models.
Here is what I downloaded from OnSemi just a month or so ago and you can see
that the date is 2003, and the BF=10000:
downloaded 9-17-2010
* Model generated on Sep 10, 03
* MODEL FORMAT: PSpice
.MODEL BADMJ21194 npn
+IS=4.02325e-14 BF=10000 NF=1.1488 VAF=10000
+IKF=0.377331 ISE=2.16244e-09 NE=2.49213 BR=0.1
+NR=1.5 VAR=1.70851 IKR=3.77331 ISC=1.00031e-16
+NC=3.99945 RB=0.1 IRB=0.1 RBM=0.1
+RE=0.00775691 RC=0.0387846 XTB=0.1 XTI=1
+EG=1.05 CJE=1.07724e-08 VJE=0.975489 MJE=0.524369
+TF=1e-08 XTF=2.16157e+06 VTF=0.184568 ITF=5.56361
+CJC=2.68609e-10 VJC=1.64862 MJC=0.242322 XCJC=0.1
+FC=0.910137 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
I see you offered a .zip file earlier in the thread and you use the MJL versions
with models identified as: mfg=OnSemi060708
Are these straight from OnSemi or did you modify them?
Just downloaded the MJL models from OnSemi and they are dated 2004:
.MODEL mjl21193 pnp
+IS=2.37302e-11 BF=92.8585 NF=0.85 VAF=1000
+IKF=7.81463 ISE=9.34142e-13 NE=1.83168 BR=1.39987
+NR=0.905395 VAR=421.163 IKR=1.8668 ISC=9.34142e-13
+NC=3.03125 RB=14.6266 IRB=0.1 RBM=0.149902
+RE=0.000682292 RC=0.146081 XTB=1.32633 XTI=1.05623
+EG=1.05 CJE=1.15773e-08 VJE=0.57352 MJE=0.417157
+TF=1e-08 XTF=1.946 VTF=17401.6 ITF=3.36265
+CJC=5e-10 VJC=0.95 MJC=0.23891 XCJC=0.999998
+FC=0.987529 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
* Model generated on Jan 25, 2004
* Model format: SPICE3
.MODEL mjl21194 npn
+IS=9.56205e-11 BF=62.3633 NF=0.858602 VAF=29.6613
+IKF=9.86004 ISE=7.00007e-12 NE=3.43749 BR=4.96358
+NR=0.925054 VAR=6.18692 IKR=4.87016 ISC=3.25e-13
+NC=4 RB=11.0204 IRB=0.1 RBM=0.1
+RE=0.000675706 RC=0.124974 XTB=0.150823 XTI=1.00001
+EG=1.11955 CJE=1.70807e-08 VJE=0.4 MJE=0.520397
+TF=1e-08 XTF=47.3046 VTF=1.88154 ITF=0.560261
+CJC=5e-10 VJC=0.95 MJC=0.238884 XCJC=0.800727
+FC=0.8 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
* Model generated on Jan 25, 2004
* Model format: SPICE3
BTW, if you just add .inc transistors.txt to your sims then there is no need for users
to modify their spice libraries.
Last edited:
Hi Pete,
I used models that I generated for the 21192/94 devices. The ON Semi models are awful. Andy_c pointed this out quite awhile back and inspired me to do those models myself. In fact, the need to do those models for my book simulations was what inspired Chapter 20 on how to create SPICE models. The dates on those model files after the mfg Onsemi are the dates when I finalized those models. I did not create models for the 243/253 for the book simulations because they tend not to have as much effect on the results (and time was limited), but I know they are not great.
The supplemental book information that I will be putting up on my website will include models tweaked by me for most of the transistors used in the book circuits. Like any models, they will not be perfect, but they will have been tweaked by me to the point where I trust them, and they will be based on some measurements of real devices of each type. I'm still tweaking them before I post them.
This way, the ready-to-run downloadable simulations will yield results similar to those I obtained in the book simulations.
I also created some EKV models for MOSFETs so that I could obtain more trustworthy MOSFET output stage simulations.
Cheers,
Bob
That explains it, I think it would be good if you identified them as something like mfg=BobC060708 since they are not from OnSemi after all.
Thanks Bob, for the SPICE models it is a real pain not having good models and also for the chapter on checking and improving them, I'm sure the procedures will be real handy in the future.
I'll try to duplicate your distortion figures. The very high levels of distortion surprised me for the simple topologies since we know that similar amps were produced with far better and reasonable performance. Even the Citation 12 had less than .1% THD20 at full output. What jumps out in Figure 3.1 is the large Cdom cap and you give a hint that there is slew rate limiting at 20KHz full power. 300 pF is rather large, most would use something like 100 pF at that tail current and with no degeneration which would provide a significantly better slew rate of 10V/uS. We would of course want to check stability.
The Citation 12 tail current is about 40V/8.2K = 4.9 mA or 2.45 mA per transistor, the Miller cap is 150 pF, and the slew rate: 2.45/150pF = 16.3 V/uS
It seems to me that it would have been good to offer an example of distortion that results from slew rate limiting but that it should be treated separately from distortion caused by transistor non-linearity as it otherwise clouds the understanding.
Thanks Bob, for the SPICE models it is a real pain not having good models and also for the chapter on checking and improving them, I'm sure the procedures will be real handy in the future.
I'll try to duplicate your distortion figures. The very high levels of distortion surprised me for the simple topologies since we know that similar amps were produced with far better and reasonable performance. Even the Citation 12 had less than .1% THD20 at full output. What jumps out in Figure 3.1 is the large Cdom cap and you give a hint that there is slew rate limiting at 20KHz full power. 300 pF is rather large, most would use something like 100 pF at that tail current and with no degeneration which would provide a significantly better slew rate of 10V/uS. We would of course want to check stability.
The Citation 12 tail current is about 40V/8.2K = 4.9 mA or 2.45 mA per transistor, the Miller cap is 150 pF, and the slew rate: 2.45/150pF = 16.3 V/uS
It seems to me that it would have been good to offer an example of distortion that results from slew rate limiting but that it should be treated separately from distortion caused by transistor non-linearity as it otherwise clouds the understanding.
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Hi Pete,
Actually, in the models I'll be putting up, I did decide to designate the mfg as CA060708 (for Cordell Audio). There is potential confusion either way, as dropping the Onsemi represents a loss of information of sorts.
I chose 500 kHz closed-loop bandwidth for all of the amplifiers in Chapter 3 as a safe and consistent value, and this resulted in the 300 pF Miller capacitance. With about 2.45 mA/transistor, it looks like the calculated closed-loop bandwidth for the citation 12 would be over 2 MHz in theory, way too dangerous.
However, note the 390 ohm base-emitter resistor on the VAS transistor, suggesting that if its Vbe is 0.7V, then the standing current for the LTP transistor driving it is really only about 1.8 mA, suggesting a nominal LTP imbalance. This would result in a 12V/us slew rate in the ideal case, still much more than the simple amplifier that I showed, but with an apparent dangerously high closed loop bandwidth. The real transistors used may make the idealized closed loop bandwidth estimates wrong, however.
You might want to simulate the Citation 12 and see what you get. I could be wrong, its still early in the morning.
Cheers,
Bob