john curl said:
Hi John,
I'm sorry, we seem to have lost sync in our communication. In my earlier post that I wanted your opinion on, I indicated that the OnSemi RETs looked a bit better overall to me than the Sankens. They also appear to be cheaper, easier to get, and in a friendlier package. So I was wondering if you agreed with those impressions, and if you had used them or considered using them in your new designs. Or am I overlooking something favoring the Sankens that still makes them a better choice?
Thanks,
Bob
After your input, Bob, I called my boss at Parasound to get pricing info, and the 'source' of the oscillation of the JC-1 during the review test. He didn't know the prices exactly, but please consider: We buy in lots of 100,000. You cannot compete, and your price will be higher. Personally, we have had VERY good luck with the Sanken transistors, (his experience) and my boss would not change without good cause. Not even for me.
Now when it comes to the mysterious oscillation, why don't you contact JA yourself? Say that I said it was OK. I would like to know too. Report back, if you can get a useful answer.
Now when it comes to the mysterious oscillation, why don't you contact JA yourself? Say that I said it was OK. I would like to know too. Report back, if you can get a useful answer.
Why I hate Vertical MOSFETs
Well, its a slow day here, so I thought I'd stir the pot a bit.
John Curl has suggested that I have an unfair bias favoring Vertical MOSFETs. I must admit, I do like the little buggers. But in the interest of fairness and full disclosure, I have put together a list of things that I don't like about them.
Low transconductance
The transconductance of a MOSFET is about ten times smaller than that of a BJT at the same operating current. This means that in a push-pull Class-AB output stage, crossover distortion will be higher as a result of transconductance droop in the crossover region unless the MOSFET output stage is operated at a much higher idle bias current. This is the reason that some authors claim that MOSFETs are less linear than BJTs. This effect can be greatly mitigated by the use of error correction circuits, but that amounts to an increase in circuit complexity and additional stability issues to manage.
High frequency parasitic oscillations
The vertical MOSFET is about ten times as fast as even a RET BJT, in terms of equivalent device ft. This is both a blessing and a curse. This leads directly to an increased propensity for vertical MOSFETs to become involved in parasitic oscillations. This matter is further exacerbated when vertical MOSFETs are connected in parallel, because the HF circuit becomes more complicated and there are more opportunities for oscillator topologies and resonances to be formed. The bottom line is that a higher level of high-frequency design expertise, layout care and HF snubbing is required for MOSFET output stages.
Need for fast short-circuit protection
The vertical MOSFET is capable of conducting enormous amounts of current while requiring virtually no drive current to do so. There is very little in the way of self-protective behavior, such as high-current beta degradation in BJTs. While vertical MOSFETs are quite robust in terms of SOA (which is usually thermally limited by peak die temperature), they can be quickly destroyed by the extremely high currents that can occur in the presence of a short circuit. Their destruction under these conditions can be faster than a fuse or a relay, often leading to the need for fast electronic short-circuit protection.
Fragile gate requires protective measures
The gate of the vertical MOSFET is essentially like a capacitor of a couple of nanofarads with a very thin dielectric. Because of the capacitance, it is not terribly sensitive to ESD, but its breakdown voltage of only about +/- 20V means that instant destruction can occur under any condition, d.c., or a.c., that causes this maximum voltage to be exceeded (resulting in gate oxide punch-through). This means that the circuitry driving the gate of the MOSFET must never be allowed to cause the Vgs_max to be exceeded, even under fault conditions. It is also important that any protective measures applied at the gate, such as zener diodes, not exacerbate the possibility of high frequency parasitic oscillations. Finally, it is possible under certain parasitic oscillation conditions for the internal device gate-source voltage to exceed that at the device terminals, leading to gate oxide breakdown. This is one reason why it is so important to avoid parasitic oscillations in vertical MOSFETs.
Thermal Runaway
The Vertical MOSFETs are not immune to thermal runaway. They require thermal tracking bias compensation, as do BJTs. This is because the temperature coefficient of drain current is positive up to fairly high currents in the Ampere range, well above normal Class-AB idle current values. Their bias points are, however, less vulnerable to temperature dynamics than those for BJTs.
High input impedance invites poor design
MOSFETs are relatively easy to drive as a result of the high input impedance at their gates. This is certainly true at d.c., but less true for a.c. at higher frequencies due to the capacitance seen looking into the gate. Even with this capacitance, they are still easier to drive at high frequencies than BJTs, but unfortunately this can invite some designers to try to drive MOSFETs directly from the VAS. Skilled designers using a beefy VAS can do this successfully, but the average designer who drives MOSFETs directly from the VAS may suffer poor performance. In most situations, the MOSFET should be buffered from the VAS by an emitter follower or other type of buffer stage.
Hopefully this list will result in some good discussion. If I have left out any other disadvantages of the vertical MOSFETs, maybe some others will help fill in the blanks.
All devices are imperfect and have dragons which we designers must slay. Often our decision about which device to use depends on which dragons we choose to slay.
Cheers,
Bob
Well, its a slow day here, so I thought I'd stir the pot a bit.
John Curl has suggested that I have an unfair bias favoring Vertical MOSFETs. I must admit, I do like the little buggers. But in the interest of fairness and full disclosure, I have put together a list of things that I don't like about them.
Low transconductance
The transconductance of a MOSFET is about ten times smaller than that of a BJT at the same operating current. This means that in a push-pull Class-AB output stage, crossover distortion will be higher as a result of transconductance droop in the crossover region unless the MOSFET output stage is operated at a much higher idle bias current. This is the reason that some authors claim that MOSFETs are less linear than BJTs. This effect can be greatly mitigated by the use of error correction circuits, but that amounts to an increase in circuit complexity and additional stability issues to manage.
High frequency parasitic oscillations
The vertical MOSFET is about ten times as fast as even a RET BJT, in terms of equivalent device ft. This is both a blessing and a curse. This leads directly to an increased propensity for vertical MOSFETs to become involved in parasitic oscillations. This matter is further exacerbated when vertical MOSFETs are connected in parallel, because the HF circuit becomes more complicated and there are more opportunities for oscillator topologies and resonances to be formed. The bottom line is that a higher level of high-frequency design expertise, layout care and HF snubbing is required for MOSFET output stages.
Need for fast short-circuit protection
The vertical MOSFET is capable of conducting enormous amounts of current while requiring virtually no drive current to do so. There is very little in the way of self-protective behavior, such as high-current beta degradation in BJTs. While vertical MOSFETs are quite robust in terms of SOA (which is usually thermally limited by peak die temperature), they can be quickly destroyed by the extremely high currents that can occur in the presence of a short circuit. Their destruction under these conditions can be faster than a fuse or a relay, often leading to the need for fast electronic short-circuit protection.
Fragile gate requires protective measures
The gate of the vertical MOSFET is essentially like a capacitor of a couple of nanofarads with a very thin dielectric. Because of the capacitance, it is not terribly sensitive to ESD, but its breakdown voltage of only about +/- 20V means that instant destruction can occur under any condition, d.c., or a.c., that causes this maximum voltage to be exceeded (resulting in gate oxide punch-through). This means that the circuitry driving the gate of the MOSFET must never be allowed to cause the Vgs_max to be exceeded, even under fault conditions. It is also important that any protective measures applied at the gate, such as zener diodes, not exacerbate the possibility of high frequency parasitic oscillations. Finally, it is possible under certain parasitic oscillation conditions for the internal device gate-source voltage to exceed that at the device terminals, leading to gate oxide breakdown. This is one reason why it is so important to avoid parasitic oscillations in vertical MOSFETs.
Thermal Runaway
The Vertical MOSFETs are not immune to thermal runaway. They require thermal tracking bias compensation, as do BJTs. This is because the temperature coefficient of drain current is positive up to fairly high currents in the Ampere range, well above normal Class-AB idle current values. Their bias points are, however, less vulnerable to temperature dynamics than those for BJTs.
High input impedance invites poor design
MOSFETs are relatively easy to drive as a result of the high input impedance at their gates. This is certainly true at d.c., but less true for a.c. at higher frequencies due to the capacitance seen looking into the gate. Even with this capacitance, they are still easier to drive at high frequencies than BJTs, but unfortunately this can invite some designers to try to drive MOSFETs directly from the VAS. Skilled designers using a beefy VAS can do this successfully, but the average designer who drives MOSFETs directly from the VAS may suffer poor performance. In most situations, the MOSFET should be buffered from the VAS by an emitter follower or other type of buffer stage.
Hopefully this list will result in some good discussion. If I have left out any other disadvantages of the vertical MOSFETs, maybe some others will help fill in the blanks.
All devices are imperfect and have dragons which we designers must slay. Often our decision about which device to use depends on which dragons we choose to slay.
Cheers,
Bob
Bob Cordell said:
I have played with LTspice, but haven't weaned myself from
Microcap, since I've played with it since version 1. I bought
version 1, but have only used the free crippled student versions
since.
Mosfet Models? I don't need no stinkin' Mosfet models!
Nelson Pass said:
I think that in the interest of symmetry we should leave that to John 🙂.
Cheers,
Bob
Nelson Pass said:
.........
Mosfet Models? I don't need no stinkin' Mosfet models!
now you're nasty...........
btw:
http://www.blic.co.yu/culture.php?id=211
Zen Mod said:
I see from the same site that "Serbian girls are beautiful". They
did not, however, provide any evidence to support that claim.
😎
Nelson Pass said:
naah............
ya know what they say.......beauty is in eyes of beholder..........
I am - as someone to whom Pass Labs products are pretty good looking , certainly not qualified to judge those delicate issues
edit:
ps. serbian girls itself supports that claim
Zen Mod said:
Is it just plain ol me, or does that Jar-face musician look like Austin Powers without a mojo shaver?
Some may view the current price level of verticals as their biggest drawback, seen different tags at the time when scare few used them.
jacco vermeulen said:
it wasn't me- but Papa who seek for beauty oriented links, beneath original one ;
so- I can't comment on that particular one ......
I found this quite a problem. If something goes wrong, all the mosfets will be destructed in fraction of an eye blink. Bipolars usually give some warnings (with enough time to be notified by us).
Mr. Cordell, have you got references how to make mosfet protection cct that can handle mosfet's destruction fastness?
It has been my experience that bipolars give more time before breaking and are therefore easier to protect with relays or circuit breakers.
lumanauw said:
How's about high source resistor values, to mimic the RDSon level of a Lateral MOSFET ?