Nostalgia. From a technical perspective there's no reason - my friends (founding employees of Purifi Audio, no less) would be shaking their heads and rolling their eyes. 🤣
And unless I find a robust solution, I will indeed just make a new print for two pairs of Toshiba devices with emitter resistors and no output cascodes and call it a demi-cascode and be happy.
Best Regards
Jens
There is another issue with this cascode. The base of the transistors Q116 and Q119 is fed with constant current source about 28ma. Assuming the beta is 100, the max output current is 2.8A.
[EDIT] The red led is about 1.7 vdrop. Thus the CCS is about 40ma, the max output is about 4A assuming beta is 100. It could work but it is too small as I like.
[EDIT] The red led is about 1.7 vdrop. Thus the CCS is about 40ma, the max output is about 4A assuming beta is 100. It could work but it is too small as I like.
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thd average, clipping poor, stabilty poor, slew mediocre ................ ah well, maybe you like the sound
xy lm3886 review
I measure 48 mA (went for a red LED with high Von) by measuring the voltage across R132.
The design anticipates this, with Darlington devices (MJ11015/11016) for the cascodes, guaranteed minimum beta of 1000 at 20A. Now, the speed of those devices is a different matter. The original article measures 17 A peak out for a 2 Ohm resistive load (in a single sine wave period)
What annoys me is that, for these amplitudes, everything looks fine on the negative cascode. It's just the positive side which gets something wrong. Also, I can produce near rail to rail square waves with no problem on the cascode voltage, as long as the load is 8 Ohm resistive. On the other hand, low impedances with capacitive loads are my primary use case, so I don't want to go with an amp with a measured problem.
Best Regards
Jens
The emitter voltage going higher than the base voltage implies that no current is being drawn. The collector-base capacitance of Q115 is coupling the rising edge of AmpOut to TO_CC_C through R131.
A better output stage would not connect the junction of R131 and R133 to AmpOut. That way, the driver transistors will remain in class A.
Ed
Oh, and before I condemn only the positive cascode, let's look at the response of both cascodes when driving 25 Vpp square wave into 8 Ohm || 1 uF
The positive cascode voltage, TO_CC_C in red
and the negative, TO_EE_C
Not stellar, either.
The output is sticking to some semblance of normality
but the internal node, S2in1, is struggling
Best Regards
Jens
The positive cascode voltage, TO_CC_C in red
and the negative, TO_EE_C
Not stellar, either.
The output is sticking to some semblance of normality
but the internal node, S2in1, is struggling
Best Regards
Jens
How much current is on the VAS? There must be fundamentally wrong somewhere. I would suggest go back to simulation.
PS: I suspect the VAS is running out of current so that it could not charge the miller cap. When that happens, you will see something like parasitic oscillation.
PS: I suspect the VAS is running out of current so that it could not charge the miller cap. When that happens, you will see something like parasitic oscillation.
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Well, simulations are showing an enormous amount of information. How much of it is useful, I do not know. Clearly, the last three transistors (Q109, Q114 and Q115) are going to notice the load differently.
The VAS pumps the voltage up with no current limit (Q109 just adds more current), but the slew-rate affects the amount of ringing on the output which in turn affects the peak current.
Here we have the 8 Ohm || 1 uF load, but a square wave which is more than 10 times the amplitude of the one I've been watching the most (the 6 Vpp). This is 80 Vpp, and the problem is only just showing up in simulation. For the 6 Vpp level that I'm testing, and where TO_CC_C is showing peaking, nothing shows up in simulation at all.
The two plots below are different in that the C101 capacitor is set to two different values. If you look closely, you will see that this only affects the internal voltages, the voltage on the load has the same slew-rate...
Various stages are running out of current with the smaller input capacitor, that's for sure, but it looks limited to the output and the driver. The bottom VAS device, Q112, is almost running out of bias, but not quite. The driver, Q114 runs out badly (current is negative, briefly, in the dip after the first peak. The output device, Q115, has wrong phase and runs out of current, hard, and then comes back.
To be honest, the device models are a random mix of models I found on the Internet, some of which are not even intended to be for the actual devices. So, the level of detail we are looking at is far too great to trust in the simulation. The plots below are for 50 us time window around the rising edge, identical to several of the plots in post #3.
First, far from broken, input cap C101 set to 1n5 (like in the Amp I built). The output device is able to respond in a linear fashion to the demanded input slew rate.
Then the demanded slew rate in increased a little by reducing the C101 to 1n0. The output peak more than doubles in Q114 (from 450 mA peak to 1.1 A peak). The output Q115 tries to deliver twice the current, and gets the level wrong. The output current settling is not only saturating the device it is also wrong in time - the peak starts earlier and then settling ends up at the same place as with the slower input (because we are seeing the output LC tank defining the waveform and not the amp). The timing of the negative and positive halves of the rising edge is different, a sign of the electronics operating beyond the mode we would like them to be in.
While I haven't show it here, the first stage of the VAS is quite far from running out of bias current, with an excursion less than 50% of the standing current and the same amplitude in the two cases, but a far more busy looking waveform in the second case where the output is limiting. This is definitely a potential problem, but the simulations is not showing it.
While the simulation could well be wrong about most of the dynamics of the signals at the time of the rising edge, I believe it regarding the required output load current and regarding the bias currents. The output slew rate is similar, between measurement and simulation. (given that the slew rate is intended to be set by C101, that is no surprise.) The bias currents check out when doing DC measurements on the amp.
It's the fine detail, which devices switch off and when, which I do not trust so much.
So, the simulation needs to be kicked with a signal of more than 10 times greater amplitude, and the input slew rate increased 50%, before a problem shows up. If the problem I see in these simulations is the problem I measure, I just do not know.
Best Regards
Jens
The VAS pumps the voltage up with no current limit (Q109 just adds more current), but the slew-rate affects the amount of ringing on the output which in turn affects the peak current.
Here we have the 8 Ohm || 1 uF load, but a square wave which is more than 10 times the amplitude of the one I've been watching the most (the 6 Vpp). This is 80 Vpp, and the problem is only just showing up in simulation. For the 6 Vpp level that I'm testing, and where TO_CC_C is showing peaking, nothing shows up in simulation at all.
The two plots below are different in that the C101 capacitor is set to two different values. If you look closely, you will see that this only affects the internal voltages, the voltage on the load has the same slew-rate...
Various stages are running out of current with the smaller input capacitor, that's for sure, but it looks limited to the output and the driver. The bottom VAS device, Q112, is almost running out of bias, but not quite. The driver, Q114 runs out badly (current is negative, briefly, in the dip after the first peak. The output device, Q115, has wrong phase and runs out of current, hard, and then comes back.
To be honest, the device models are a random mix of models I found on the Internet, some of which are not even intended to be for the actual devices. So, the level of detail we are looking at is far too great to trust in the simulation. The plots below are for 50 us time window around the rising edge, identical to several of the plots in post #3.
First, far from broken, input cap C101 set to 1n5 (like in the Amp I built). The output device is able to respond in a linear fashion to the demanded input slew rate.
Then the demanded slew rate in increased a little by reducing the C101 to 1n0. The output peak more than doubles in Q114 (from 450 mA peak to 1.1 A peak). The output Q115 tries to deliver twice the current, and gets the level wrong. The output current settling is not only saturating the device it is also wrong in time - the peak starts earlier and then settling ends up at the same place as with the slower input (because we are seeing the output LC tank defining the waveform and not the amp). The timing of the negative and positive halves of the rising edge is different, a sign of the electronics operating beyond the mode we would like them to be in.
While I haven't show it here, the first stage of the VAS is quite far from running out of bias current, with an excursion less than 50% of the standing current and the same amplitude in the two cases, but a far more busy looking waveform in the second case where the output is limiting. This is definitely a potential problem, but the simulations is not showing it.
While the simulation could well be wrong about most of the dynamics of the signals at the time of the rising edge, I believe it regarding the required output load current and regarding the bias currents. The output slew rate is similar, between measurement and simulation. (given that the slew rate is intended to be set by C101, that is no surprise.) The bias currents check out when doing DC measurements on the amp.
It's the fine detail, which devices switch off and when, which I do not trust so much.
So, the simulation needs to be kicked with a signal of more than 10 times greater amplitude, and the input slew rate increased 50%, before a problem shows up. If the problem I see in these simulations is the problem I measure, I just do not know.
Best Regards
Jens
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Speed of output device is not my issue. Speed of entire cascode system is what I cannot get to cover the needs of the already very fast output devices. And changing to a FET based cascode is not an option I am entertaining.
Did you use the FETs for cascodes?
One area where the FET is better suited is that the datasheet actually mentions package inductance. I'm sure you will all join me in being entirely unsurprised that the MJ11015/11016 model I found does not have inductance in it. With main devices fT of 60 - 80 MHz running in Class AB and driver fT of 100 MHz, package inductance is not a trivial issue in the device which must provide the output current...
Best Regards
Jens
Did you use the FETs for cascodes?
One area where the FET is better suited is that the datasheet actually mentions package inductance. I'm sure you will all join me in being entirely unsurprised that the MJ11015/11016 model I found does not have inductance in it. With main devices fT of 60 - 80 MHz running in Class AB and driver fT of 100 MHz, package inductance is not a trivial issue in the device which must provide the output current...
Best Regards
Jens
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Hello,
I am now leaning more and more in this direction, with one minor modification: Using no cascode at all, but a voltage regulator to bring the output supply voltage down far enough for a single device with emitter resistor to be viable. The regulator will need to be fast, though. That's a much more ordinary problem to have, though, then the design of a proper floating voltage source with the required specs for the original design.
This is simply a reflection of my use case. I have a hybrid dynamic/electrostatic speaker with 4 Ohm nominal impedance. I do not need to play seriously loud. On the other hand, I do not want a poorly slewing cascode to start kicking the amp feedback loop around - to me, that would be self evidently worse than whatever are the issues that the cascode may fix when driving a purely Ohmic test load.
I don't want to start changing output devices or supply transformer. So, with no cascode to bring down the max output swing, I'm looking at, say, 46 V supply, which - for 4 Ohm load - looks unreliable for a single pair of the fast Toshibas.
Looking at the SOA for the fast Toshibas, it all makes enough sense for me to fire up the simulator. Say, a supply voltage of 35 V, a load impedance of 4 Ohm and an output voltage of 20 V. The device has 15 V across it and 5 A running through it. This is comfortably inside the DC area of the SOA (it's only 75 W dissipated) and the device temperature limit 80-some deg C. And that's at DC. (With supply 46 V, load voltage 26 V, we would dissipate 130 W in the output device which is alarming.)
I will want a simulation with a transistor, a behavioural VAS and a load to get the detailed dissipated power levels and specs for the supply regulator, but I'm not afraid anymore.
A copy of Cordell's "Designing Audio Power Amplifiers" is making its way to me through our superb library system. With that I hope to avoid a few of the obvious mistakes. And I will make sure to start testing with open feedback loop and making sure that the various stages stay out of saturation for square waves into nasty loads, and AC response stays sane, before closing the loop.
Thanks for your time and the interesting and informative comments.
Best Regards
Jens
Worst case peak dissipation for a resistive load is when the output is half way up the rail. That is, at 17.5V. That’s only 76W. When the load is fully reactive, it can QUADRUPLE, going to 306W. It never gets that bad in practice, and the compromise value of 153W is usually used for a 30 degree load. Impedance minima can go below 4 ohms, but that ALWAYS happens at zero phase, and any reactive impedance rises from that. And the duration of the reactive portion of power dissipation is less than a quarter of a cycle. Considering the time factor, this is fine for a 150W transistor, if it is full power capable at the 35V rail. But that’s probably as high as you should go on the rail.
MJ11015/6 are just fine as regulators. One does not NEED hyper fast transistors there. You need a small bypass cap on the output side, and a big one on the supply side. Yeah, there will be some small ripple and disturbances under large transient loads. But small in magnitude compared to the supply. If the output EFs have enough supply rejection to deal with the cascode’s nastiness and only slightly upset things in the output waveform, converting to a 35V regulator ought to make them totally invisible, and way into the noise floor on a spec-an.
MJ11015/6 are just fine as regulators. One does not NEED hyper fast transistors there. You need a small bypass cap on the output side, and a big one on the supply side. Yeah, there will be some small ripple and disturbances under large transient loads. But small in magnitude compared to the supply. If the output EFs have enough supply rejection to deal with the cascode’s nastiness and only slightly upset things in the output waveform, converting to a 35V regulator ought to make them totally invisible, and way into the noise floor on a spec-an.
Impedance of electro stats goes low at high frequency. Where output power is low (if you value your hearing, and listen to music not test tones), the up to 306W dissipation is very short duration (few microseconds). For practical purposes, one can use the switching SOA, which is usually pretty square. As frequency drops into the midrange, impedance rises so the peak dissipations go way down when the pulses get long. The bottom end would be handled by a conventional woofer, usually. The amplifier does need to be stable and well behaved with a heavy capacitive load, which this basic amp should be.
So, if I wanted to get going quickly, I could just change D101 to a 36 V Zener diode (2 W or more), move the cold point (bottom of R132 in this schematic) to Ground and add a cap to the TO_CC_C node which would now be the regulator output?
A tempting thought 🤣
Seriously, I will certainly simulate the discrete Darlington version of this, since I have TTC004B/TTA004B and 2SC2565/2SA1095(1) to spare. The faster devices should be able to open/close faster, reducing ripple on the output under evil load conditions. And going away from the TO-3 packaged MJ types will allow me to mount this directly on the back of a heatsink and not have to horse around with an angle bracket.
I had spent a little time thinking about active regulation circuits, but actually getting something that would respond faster/better than the above and still be simple to design is something that I know would be a challenge.
Best Regards
Jens
(1) or I could buy 2SC5200/2SA1943 in similar packages and with up to date transistor models from Toshiba. They are cheap enough.
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I’d probably go to 37V, using a 15 and 22V zener in series. At 15A, the Vbe is probably around 2V. Two 18’s would work too, if that’s what’s on hand. The output side bypass cap should be small - 10 uF or so. You don’t want a large hungry cap on the regulators output at start up as it’s collector current will spike. Definitely bypass the zener with around 100 uF. That will kill zener noise at high frequency, and slow the rate of rise at start up so the 10 uF cap won’t present an SOA problem for the darlington. They have the reverse diode built in, which would normally be needed with most regulators.
Look at the design of a good output stage. It has:
- EF3 to provide so much current gain that Hfe does not matter much
- Parallel pairs of output transistors to reduce dissipation and distortion
- Pre-driver and driver transistors operate in class A. Only the output transistors run in class AB.
- Emitter resistors are chosen for lowest distortion with adequate thermal margin
I notice that this amplifier uses two-pole compensation, which may not respond well to square waves. Switching to one-pole compensation should fix that.
Ed
Hi Ed,
I will study Cordell's book. Off the top of my head, the open-loop gain of this amp is some 60 dB and a -3 dB frequency of 20 kHz gives 20 MHz as unity-gain. While all the devices have fT higher than that, some compensation seems in order. I don't know if first order will bring things under control. That's something I can read about, and then experiment with (I hope the book has advice on measuring open-loop - simulations are just a guideline for this project, as I have found).
Best Regards
Jens
I will study Cordell's book. Off the top of my head, the open-loop gain of this amp is some 60 dB and a -3 dB frequency of 20 kHz gives 20 MHz as unity-gain. While all the devices have fT higher than that, some compensation seems in order. I don't know if first order will bring things under control. That's something I can read about, and then experiment with (I hope the book has advice on measuring open-loop - simulations are just a guideline for this project, as I have found).
Best Regards
Jens