B1 Buffer Preamp

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#722
Yeah.
I have done one such basic buffer circuit already.
Even posted it here in Pass forum ...
And I know just what the circuit will be like. It is in my head.

The hard part is to find that N-JFET with like 5-10 mA at Vgs ~0.7 Volt.
And that qualifies good for Audio use (low noise etc)
Last time I tested some N-JFETs in my sim library, I did not run in to one suitable.
But I only had patients to try like 5% of all available.

Will take half a day to try all 😀
 
#723
Lineup shot me down..........

Dear Lineup,

............you mean two more reasons.

Well in some people think Mr.Pass is god (notice I spelled that with a small 'g' ),and that sould be reason enough but it would be nice to do a comparison of your respective topologies.

Best regards,

Jam :bawling:
 
#725
Professor Smith

I have split off many of Professor Smith's questions and the answers to here:

http://www.diyaudio.com/forums/showthread.php?s=&threadid=130708&perpage=25&pagenumber=1

The new thread should be used for all questions by Professor Smith and the answers to them. Prof Smith, don't post more questions in this thread, that way they will all be in one place and be of the most use to other people starting out, and this thread won't be so scattered.

:captain:
Variac
 
#726
Absolutely nothing wrong with this implementation

It's ZMs modified schematic with dip-8 sockets for the jfets and 9V battery power. I was going to try 2SJ108 GR in there, but I broke the tabs off the pot (fake alps) and haven't gotten around to replacing it, so it's out of commission at the moment

(AP 1.7 on the left, F4 on the right)
An externally hosted image should be here but it was not working when we last tested it.



An externally hosted image should be here but it was not working when we last tested it.


Thank you Nelson Pass
 
#729
twitchie said:
Absolutely nothing wrong with this implementation

It's ZMs modified schematic with dip-8 sockets for the jfets and 9V battery power. I was going to try 2SJ108 GR in there, but I broke the tabs off the pot (fake alps) and haven't gotten around to replacing it, so it's out of commission at the moment

Thank you Nelson Pass
Click to expand...

Very nice, did you listen to it? See about offset before the output capacitors. Should be minimal with matched fets. Tap off from there to output and listen without them caps too. It sounds better.
 
#731
Had a discussion with John Curl about that recently. We concluded that it must be some Idss related sweet spot. For 7mA Idss that I used (most common mean average is 7-8mA for BL batches in my experience) it is subjective performance wise valid. I have carefully arrived to +/- 10V. For other Idss picked devices it may be a bit different. Since I haven't made another non caps B1 to compare with say 10mA devices, I just recommend trimmers for the supplies and some auditioning with different symmetric voltages. It pays off.
 
#732
salas said:
Had a discussion with John Curl about that recently. We concluded that it must be some Idss related sweet spot. For 7mA Idss that I used (most common mean average is 7-8mA for BL batches in my experience) it is subjective performance wise valid. I have carefully arrived to +/- 10V. For other Idss picked devices it may be a bit different. Since I haven't made another non caps B1 to compare with say 10mA devices, I just recommend trimmers for the supplies and some auditioning with different symmetric voltages. It pays off.
Click to expand...

You are quite right. I have data on that subject, as probably does John,
although you need not assume symmetric voltages.

😎
 
#733
Thanks Nelson for contributing in this minor issue.

I don't assume symmetric supplies per se, it just happens I used such in my B1 capacitor-less coupling version example. The absolute best D to S voltage difference in such a circuit for given Idss is in focus.
 
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