Yes. This is what I meant when I said
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What is the Y axis? Is that power output, dissipation in the output? Surely there should be some current & voltage dependence in this plot.
Does this mean you did 'real life' testing on such an amp with a large reactive dummy load which would exercise the output devices beyond the DC SOA limits (in the datasheet) but within your set limits? .. and when you used a load which would move beyond your set limits, the protection worked?But it DID work as designed
For argument . If someone designed an amplifier to fail in such a may that repairs were easy and used capacitor coupling would it still cause speaker damage ? I suspect in most cases it wouldn't . Non polar caps of 220 uF 35V could be banked up . The cost would be OK . I bought some for 5 pence recently . I am sure capacitors are better than valve output transformers . Doesn't stop valve people preferring their amps to transistor amps . Mostly I have to agree if of sufficient quality .
It's dissipation in one polarity of the output (three devices), in Watts.
The DC allowed dissipation is 3 x 150W = 450W as shown in the graph.
You can also see that for rather short duration the allowed dissipation is several kilo-Watts.
Jan
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Assuming a power supply of infinite current capability then worst case scenario would be just the energy transmitted via the speaker coupling cap into the speaker (assuming the output stage failed short circuit in an infinitely small space of time). In practice most drive units would I suspect survive that without any issue given "normal" values of coupling cap and "normal" values of DC rail.
Valve coupling transformers vs caps are a different problem. Transformers are needed for impedance matching the speaker to the valve output stage in 99% of amps.
Yes I did, I tested with combinations of R and C load, with various signal frequencies and levels. Not sure about the details any more (this was 1984!); I do remember that at some point I thought I knew enough and stopped testing realising that I hadn't testing all possible combinations.
However, in my later designs I didn't use such an elaborate system. The next design had 5 parallel output devices for a 100W/8ohms design and with the lower supply and more devices detailed SOA protection is less of an issue. It had dual slope protection à la Kiwanuka and appears to be reliable.
Jan
Two good AES papers on SOA protection were presented by Eric Mendenhall.
Computer aided design and analysis of class B and class H power amp output stage 101 convention 1996 Los Angeles
abstract: ''
A brief review of the constraints and stresses on the output stage transistors of class B and
class H power amplifiers is presented. The cases considered are simple resistive loading, firstorder
reactive loading, and complex reactive loading by a real loudspeaker or electrical equivalent
model. Several simple relations are presented to aid in the thermal design &the output stage. A
way ofobtaining junction temperature vs. time for a complex power waveform is introduced. A
computer program is introduced as a design tool and tutorial aid, providing graphical and
numerical output not as easily obtainable otherwise."
Audio power amp output stage protection
conventiion paper 5695 113 convention oct 2002 lLos Angeles
ABSTRACT
This paper reviews a progression of circuits used for protecting bipolar power transistors in the output stages of
audio power amplifiers. Design oriented methods of determining the protection locus are shown in a mathematical
and graphical procedure. The circuits are then expanded from their standard configurations to allow for transient
excursion beyond steady state limits, and thermally dependent protection limits, to better match the protection
limits to the actual output stage capability. This allows the protection scheme to prevent output stage failure in the
least restrictive way.
A new method is shown for achieving a junction temperature estimation system without the use of a multiplier
Fyi
JPV
Computer aided design and analysis of class B and class H power amp output stage 101 convention 1996 Los Angeles
abstract: ''
A brief review of the constraints and stresses on the output stage transistors of class B and
class H power amplifiers is presented. The cases considered are simple resistive loading, firstorder
reactive loading, and complex reactive loading by a real loudspeaker or electrical equivalent
model. Several simple relations are presented to aid in the thermal design &the output stage. A
way ofobtaining junction temperature vs. time for a complex power waveform is introduced. A
computer program is introduced as a design tool and tutorial aid, providing graphical and
numerical output not as easily obtainable otherwise."
Audio power amp output stage protection
conventiion paper 5695 113 convention oct 2002 lLos Angeles
ABSTRACT
This paper reviews a progression of circuits used for protecting bipolar power transistors in the output stages of
audio power amplifiers. Design oriented methods of determining the protection locus are shown in a mathematical
and graphical procedure. The circuits are then expanded from their standard configurations to allow for transient
excursion beyond steady state limits, and thermally dependent protection limits, to better match the protection
limits to the actual output stage capability. This allows the protection scheme to prevent output stage failure in the
least restrictive way.
A new method is shown for achieving a junction temperature estimation system without the use of a multiplier
Fyi
JPV
The LPC43xx ADC does conversions at 400Kb/sec, that is a 2.5uS cycle. It is cheaper than the TI TMS570 R4 and inferior in any way I'm looking at. See the data sheet at pp. 81.
For the rest, yes, there are solutions for anything, including a high speed 3Gb/sec acquisition board. However I still have to see something in the digital domain that makes more sense in protecting against secondary breakdown, compared to the analog solution of two transistors and a few resistors and diodes.
BTW, I have absolutely no plans to build such a device. Others have claimed to, and I was served the "under NDA" boilerplate when asking for the details.
This ^^^. Once the second breakdown region is entered all bets are off.
That means you need to 'keep an eye' on the development of the Vce/Ic combination over time and pull the plug when you get close to the danger zone. This takes time, and it is very simple to time-bias this process. If, for instance, you are in a situation where you need to activate the protection after 10mS, you can bias it to 9mS which gives you a leisurly 1mS to activate the protection. There's really not any time pressure here.
What makes the design of such a system interesting is that all of this is dynamic. The Vce/Ic combinatios change continually, and the allowed SOA also varies with the current heat sink temperature. These are interesting issues
Jan
Issues which a digital approach easily handles. Since temperature is one of the monitored inputs, SOA derating is easily accomplished. Of course, devices with on-die temp sensing (On Semi's NJL line) are best due to the comparatively rapid response of the on-die diode to temp changes. However, even with conventional devices the uC can determine die temp rise ahead of heatsink temp rise using the measured values of Ic and Vce as well as pre-programmed values of thermal resistance.
But I wasn't suggesting it for its ADC, rather its throughput on any ADC data acquired. Clearly an external ADC would be called for to go below 1uS latency.
We ended up using separate high speed ADCs due to the lack of sufficiently high speed converters on available uC's.
Those protection schemes have well known limitations and drawbacks, which is why engineers continue to try and improve them.
Yeah, it's annoying when a company who spends their R&D money designing something doesn't want the design details posted up in a forum for all to freely use.
See my message here.
I would concede for something like "to do it's best to prevent the amp to end up in secondary breakdown". Again, for an output short, a slow protection (like a MCU with integrated ADC) will do squat, other than by blind chance. An analog protection is much more efficient.
Douglas,
I rather think your section on how the current mirror enforces balance of collector currents in the input stage should have given reference to the following article where-as far as I'm aware- it was first mentioned:
Taylor, E. F., “Distortion in Low-noise Amplifiers: 2”, Wireless World, September 1977, pg. 55.
Available here:
~ Scanned and cleaned up Wireless World Articles ~
I rather think your section on how the current mirror enforces balance of collector currents in the input stage should have given reference to the following article where-as far as I'm aware- it was first mentioned:
Taylor, E. F., “Distortion in Low-noise Amplifiers: 2”, Wireless World, September 1977, pg. 55.
Available here:
~ Scanned and cleaned up Wireless World Articles ~
You still don't understand that an output short in itself is not a problem. It's the Vce/Ic and time combination with the load current that runs through the short. An understanding of the actual SOA concept and its graphs will make that clear.
Alternatively, even with no short, you can still destroy the amp.
Just looking at the output load or short is myopic and misses the point.
Jan
Thanks Mooly . My thoughts exactly . If bi-polar caps a third optional terminal could be offered for party mode . Capacitors distort the signal far less than people think ( - 110 dB at a guess from things read in the distant past ) . An output transformer I imagine to be about - 56dB best possible performance ( that is if added to a near zero distortion amp without loop feedback ) . The valve guys never give it a second thought apart from bandwidth , if they do it doesn't fill the forums . Impedance matching is important and will be seen as the prime function . For what it's worth the Danbury designs are very good value and not horribly behind Sowter , I have used both . I have a design with Danbury output and Sowter mains as they are mechanically quieter . I am looking for a toroid to replace the Sowter as the Sowter is borrowed from another amp . Toroid is a hunch , cheaper , quieter , better . I don't know if Velleman ever sold theirs as a separate unit ?
Incorrect.
You still don't understand that if an output short happens when Vce is rather large, the resulting instantaneous collector current will throw the device into the secondary breakdown region. An understanding of the actual SOA concept and its graphs will make that clear.
Yes, IF the load is sufficientlyly low, and IF the Vce is sufficiently high, and IF the supply can deliver enough current, chances are that you find your self eventually exceeding the SOA.
Which however was not what you said.
In any case, even with a short or something close to it, time is required to build up the dissipation - it doesn't instantly spring into existence. You'd be surprised how (relatively) slow current and dissipation build up.
IIRC in the 'analog computer' type of SOA protection I posted before the output stage can absorb something like 4kW (that's 4000W) for a mS or so before giving up the ghost. Fast, but definitely not instantaneous.
Edit: I checked; it's 3.6kW for 10uS, I was too optimistic.
Edit2: my amp can easily withstand a dead short across the output jacks, provided I keep the output signal low enough. There's always some residual resistance that prevents the current to rise to infinity (if you'd have such a supply). So, again the output load is just a part of the story.
Jan
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Not much for secondary breakdown. Much more for thermal breakdown. The difference is from heating the entire chip to heating a very few and small hot spots within the silicon.
No questions about, that's absolutely possible. If you remember, the discussion was if a MCU with ADC conversion can act fast enough. No, not even close, unless the cost of the solution explodes. I've stated from the very beginning the superiority of an analog protection (against secondary breakdown) solution.
And this is exactly what I meant by "surviving by chance". You can't control when an output short occurs.
Waly, this is going nowhere. I am positive from my experience that very fast action is not necessary. Your view is that it must be, even 100nS or faster.
Since you stated you have no intention to build this, all this discussion is of limited value for you I would assume.
I can continue to repeat myself but that is of limited value for me.
Lets leave it at that, after you get in the last word I guess.
jan
Incorrect, if one wants 100% protection against secondary breakdown. Yourself
and the original promoter of the MCU solution both stated that if the devices enter the secondary breakdown region you are both toast. I don't see how this reconciles with your statement that "very fast action is not necessary".
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