I perceive that for the same silicon area and the same maximum voltage specification, a JFET will have greater transconductance than a MOSFET. Because bulk mobility (JFET) is higher than surface mobility (MOSFET).
MOSFET input devices are usually extremely high input impedances with bias currents that can be in the femto ampere region, or 10^-15. They can be useful in electrostatics research applications or in the measurement of signals in organic materials for example. Not so much being useful to consider in audio. Perhaps an interface to electret type microphones?
In terms of their construction, their acronyms say it: JFET = junction field-effect transistor. CMOS = complementary metal-oxide semiconductor. JFETs inherently include a diode junction. In normal operation it is reverse-biased to pinch off the conducting channel -- so they are normally ON devices, gotta be turned (partially) off to work properly. CMOS transistors have an insulating layer that separates the gate from the source and drain and the most commonly-found type is normally OFF. They need a voltage difference between their gate and source to begin to conduct current. That's their Vt. There ARE depletion-mode MOS devices but they aren't as common.
The presence of that oxide layer in CMOS devices has implications in terms of their noise performance. The Si/SIO2 interface can store and emit carriers, but the amount depends on the "recipe" that was used to make them. Over time they have gotten much better, but JFETs still are a better option w/regard to noise performance.
Due to their built-in junction, JFETs always will have a small amount of bias current, it's just part of the physics of a junction diode. CMOS devices theoretically don't need ANY current to flow, at least DC-wise. Their gates do have capacitance so it has to be charged/discharged as the gate voltage varies. BTW the JFET depletion region is a capacitor too.....
Opamps will have ESD-protection circuitry no matter what technology they use, and that also introduces leakage current. It can be very low, but its impact depends on what you're using the amplifier for. If you want to measure femto-amps it definitely will be a concern...
The presence of that oxide layer in CMOS devices has implications in terms of their noise performance. The Si/SIO2 interface can store and emit carriers, but the amount depends on the "recipe" that was used to make them. Over time they have gotten much better, but JFETs still are a better option w/regard to noise performance.
Due to their built-in junction, JFETs always will have a small amount of bias current, it's just part of the physics of a junction diode. CMOS devices theoretically don't need ANY current to flow, at least DC-wise. Their gates do have capacitance so it has to be charged/discharged as the gate voltage varies. BTW the JFET depletion region is a capacitor too.....
Opamps will have ESD-protection circuitry no matter what technology they use, and that also introduces leakage current. It can be very low, but its impact depends on what you're using the amplifier for. If you want to measure femto-amps it definitely will be a concern...
Here is a paper comparing Bipolar, JFET and CMOS inputs.
Regarding 1/f noise bipolar has the lowest and CMOS the highest noise.
Especially at lower frequencies.
Now bipolar has more input current noise.
So I guess all these are as good as another when it comes to the end.
https://www.ti.com/lit/ab/sboa355/sboa355.pdf?ts=1740566133028
Regarding 1/f noise bipolar has the lowest and CMOS the highest noise.
Especially at lower frequencies.
Now bipolar has more input current noise.
So I guess all these are as good as another when it comes to the end.
https://www.ti.com/lit/ab/sboa355/sboa355.pdf?ts=1740566133028
