Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

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A123

Disabled Account
Joined 2020
^^

Thanks for sharing. I'm going to have a similar architecture (SPDIF).

How do you feed 5V and 3.3V? 5V via J5? 3.3V direct to Q3?

I'm curious if you feed 5V on the Q3 side on the StationPi (J5) via GPIO or do you feed on the PI side (J3) direct to power the RPi?

You can add Maxwell SuperCaps on the RPi side? I noticed "OPTIONAL CAPACITORS" label.

These will be my first Ian Canada products so currently have no applicable experience yet.
 
iancanada

iancanada

Member
Joined 2009
twitter.com/iancanadaTT
Paid Member
dddac said:
Quick question for Ian.

I am working on getting a very high spec XO clock 45 and 49 MHz series (for these frequencies -115dBc at 10Hz) but need to define the OE pin. Now the OE pin will enable the output at logic HIGH or pull it Low when the OE pin goes LOW.... So, this XO will not be able to do a tri-state output. Hence I assume this will not work with the Q2 version FIFOPI ? But will on the Q3?

Correct ?

Alternatively I can leave pin 1 floating

What would you suggest for the FIFOPI Ian ?
Click to expand...

dddac said:
I see Ian stopped posting anything since his last post Oct 1st :confused: before that daily posts almost. Anything wrong?
Click to expand...

@DDDAC

OE logic is active HIGH. You have to use FifoPi Q3 if your XO output was tied to GND when disabled.

It would be up to if it has an internal pull up to decide PIN1 can be left floating . Please check your XO spec to make sure.

I'm so sorry for my late answer. I took a short vacation to enjoy the best season of Canada with flying my drone around.

Please see my YouTube channel:
Ian Canada - YouTube

Enjoy the beautiful autumn landscapes of Canada and the music!

Regards,
Ian
 
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T

tubo

Member
Joined 2007
A123 said:
^^

Thanks for sharing. I'm going to have a similar architecture (SPDIF).

How do you feed 5V and 3.3V? 5V via J5? 3.3V direct to Q3?

I'm curious if you feed 5V on the Q3 side on the StationPi (J5) via GPIO or do you feed on the PI side (J3) direct to power the RPi?

You can add Maxwell SuperCaps on the RPi side? I noticed "OPTIONAL CAPACITORS" label.

These will be my first Ian Canada products so currently have no applicable experience yet.
Click to expand...

Hi A123,

Yes 5v in j5, 3.3v on fifopi q3, then 5v on rpi. 3 power supplies are needed for the stationpi. you can share a 5v rail for rpi and j5. The early stationpi has no provision For supercaps..
 
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iancanada

iancanada

Member
Joined 2009
twitter.com/iancanadaTT
Paid Member
dddac said:
Thanks Ian for the confirmation.

nice videos by the way ! :cool:
In Germany you would not be able to do this like that .... :rolleyes:
Click to expand...

Thanks DDDAC, you have a very nice blog too, I'm really interested in it. I'll PM you later for more information.

To fly a drone legally in Canada, we need to have license for both drone and drone pilot. Have to follow the regulations and have to avoid any no-fly zone...
A lot of fun and limitations:D

Regards,
Ian
 
iancanada

iancanada

Member
Joined 2009
twitter.com/iancanadaTT
Paid Member
gionag said:
Someone can help me understanding if is only a problem for me or is really a bug ?

when i am using the clock divider feature on the mcfifo, all of sudden mute, no longer works between tracks in DSD (not sure about other formats, not albe to test them at the moment).
when i am not using the divider... everything works fine with the muting.

can someone else confirm that ?
Click to expand...

@gionag

How did you using the divider feature? What the status of both Mute and DSD signals?

Regards,
Ian
 
G

gionag

Member
Joined 2007
Hi Ian,
whenever i set the divider jumper to /2 on the McFifo board, the mute signal stop working after a track switch.
i am feeding it with DSD signal coming from hqplayer.
with the divider set to /1 when i stop a track, until I press play again, the mute stay active.
with a /2 or /4 divider set on the mcfifo, when i stop a track the mute glitch on for a second and then goes back to un-mute.

that's it
 
P

pz1

Member
Joined 2013
Hi Ian,


Nice to see your holiday video. Very beautiful.


I sent you a PM, please could you check?


Paul



iancanada said:
@DDDAC

OE logic is active HIGH. You have to use FifoPi Q3 if your XO output was tied to GND when disabled.

It would be up to if it has an internal pull up to decide PIN1 can be left floating . Please check your XO spec to make sure.

I'm so sorry for my late answer. I took a short vacation to enjoy the best season of Canada with flying my drone around.

Please see my YouTube channel:
Ian Canada - YouTube

Enjoy the beautiful autumn landscapes of Canada and the music!

Regards,
Ian
Click to expand...
 
T

trung224

Member
Joined 2016
Hi Ian,

I would like to ask one question about your UcConditioner and LiFePO4 power supply. I want a power supply with one bank of energy storage components (battery, supercaps) powering the application circuit and completely switching off from main AC power, while another bank is charged. Do your UcConditioner or LiFePo4 power supply work on this principle?

Thanks, Trung
 
A

A123

Disabled Account
Joined 2020
I did a search of the Model# RR71A101MDN1 embedded on the StationPi PCB (Optional Capacitors):

RR71A101MDN1 Nichicon | Mouser

https://www.mouser.com/datasheet/2/293/e_rr7-1919103.pdf

What dis do? Lowers impedance?

Looking forward to a StationPi build... Just focusing now on optional caps or possibly Super/Ultra Caps to power.


Cheers


EDIT: nvm, just read the FAQ. Recommended but not necessary. I'll order these capacitors as a throw in on my next Mouser order.
 
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