Another autobias design...

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In the scheme designed by Mr. Shinichi Kamijo there are several aspects that I thought I needed to change. First of all, I introduced an amplifier stage to reduce the errors caused by the imperfection of the comparators with transistors. Secondly, I even used the resistors from the emitters / sources transistor on the output stage. And finally I replaced the optocoupler with some current source in order not to alter the improvement brought by the error correction


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Despite all these changes to Mr. Shinichi Kamijo's design, the working principle is the same and works very well. I built it in three copies and I am very satisfied with the results. The standby current is constant, it does not depend on the temperature, the amplitude or the frequency of the signal.





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For reasons of easier troubleshooting, the amp is made on interconnectable modules. It consists of front-end, hec, autobias and output stage. I post the Hec to get an overview of how the autobias connects to that Hec at the end (which is generically drawn). The short protection of the output stage is also planted on the Hec plate. There are three pairs of drivers in parallel, considering that at a + -95V power supply with a total current through them of about 75mA, they heat up very well. The interconnection of the plates is done with ribbon cable. The autobias connects directly to the hec board.

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Maybe I should have pointed out at the beginning that this autobias is for the AB class amplifier. The idle current can be set between 100mA and 200mA per transistor with TR1 and TR2. They are mounted on the same shaft and adjust simultaneously. But they can be replaced with fixed resistors.
 
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To continue, I post the final version (at least at this moment ...) of my front-end. This is Bob Cordell's (very) slightly modified design. I chose Cordell's design for its special stability and very good parameters. The compensation is Tmc. The pair of jfet on the input (smp860) are in the same capsule. Because its maximum source drain voltage is only 20V and because the power supply is + -95V I added a second cascode stage to the entrance to reduce dissipation here, so it does not require radiators. To reduce distortion, the bases of transistors Q3 / Q4 are controlled by a signal identical to the input, so the drain / source voltage of the input jfet is kept fixed, eliminating the Early effect. Several ways can be used to achieve this goal, I chose to obtain this signal from the output signal with the help of resistors R17 and R12. I would also mention the clipping circuit whose threshold is basically determined by the power zenner U1 and U2. In this case they are 75V to achieve a clipping of about 75V-76V. Considering that the hec (Hawksford error correction) stage decreases by about 10V, a clipping of the output signal is cca 65V-66V. The O1 optocoupler provides a signal to the logic block when the cliping comes into action. The current through the input differential is 2mA and through the vas transistors is 10mA . The vas transistors and the current generator require cooling. The coupling with the other stage is made by ribbon cables.
I physically made 6 front-ends (for 3 amps). They all work the same. I specify this to emphasize that the parameters obtained are NOT something isolated, obtained by chance or possibly by mistake (hi). No, the reproducibility is very good. Obviously, with other pcb there may be differences. But the one I made is not a secret, it is available in eagle for those who are interested. To cool the vas transistors, I chose the version from the picture, they will be mounted near the final stage, on the same radiator. That's the concept of the amp. But they can also be mounted on the other side of pcb with independent individual radiators. The pcb is cca 70mm / 92mm.
 

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I have added the z5 and z6 zenners to protect the di79l06 and di78l06 voltage regulators, which may exceed the maximum permissible 30V at the input at the time of power-up. It hasn't happened yet, but what is safe is safe ...
 

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