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Amanero Isolator/Reclocker GB

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#845
deanoUK said:
Why do you need to desolder them ?
They are not easy to desolder and may not survive the process.

When I soldered my XOs I placed a small piece of wire under each pad so you can slide the wire out to desolder.
Click to expand...

Crystek is on Buffalo DAC and this afternoon I removed it successfully with ordinary soldering iron and piece of copper foil 0.2mm thick.
I tried to update firmware today but pin 11 continues to "misbehave" so nothing new. I guess I will solder 98 xo on x1 position then.
 
#846
Speaking of XO's, Im in the process of ordering parts (yet to receive the board) and have a quick question. The schematic shows the XOs Output Enable pin, as pin 1. Yet the Si590 is one of the recommended XOs - which uses pin 2 as OE. It seems teh Si591 uses pin 1.

So whats the correct part? 590 or 591? and before i seriously stuff up, would I be correct presume its the CMOS 3.3v version I need.
 
#847
The Si590 CMOS, Digikey part number & description:
590CD-ADG-ND, OSC PROG 3.3V CMOS HIGH 7PPM.
You will also have to specify the frequencies they are to be programmed to, ie 90.3168 & 98.304 MHz.
Although they have 6 pins only pins 1,3 4 & 6 are used 2 & 5 are not connected, the pads on the SO3 board match these "outer" pads.
 
#849
acko said:
There are a few things to consider:
1. Cost saving plus one less switching component on board.
2 The full XO frequency goes into the isolator chip (IL712) if Postemi divider bypassed. e.g. 98Mhz going into IL712 instead of the divided 49.xx or 24.xxMhz
3. Potsemi FF on the board also buffers the XO output. If bypassed then the IL712 loads the XO with its input capacitance-this value is not specified for Il712. Could have some effects.

Anyway, we need to experiment further to confirm.
Click to expand...

IL721 specs show min input pulse width of ~10ns. So not advisable to pass 90.3168/98.304MHz clock (5ns pulse) through it.

Same goes for 45.xxx/49.xxx Mhz clock (~10ns)

Best to let the external Potesemi FF divide to 22.xxx/24.xxxMHz (~20ns pulse) before clocking Amanero.
e.g. for 90.xxx/98.xxxx XO use div/4 FF and set Amanero to accept 22.xxx/24.xxxMHz ext. clock
 
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#850
smanz said:
Hi Acko.

Reclocker AKL-AMN-SXX bom have a very important mistake. For U1, U9, Bom says IL715-3E, but the correct reference is IL175-E, without digit 3. I ordered to Farnell IL715-3E, and the case is too small.
Click to expand...

Same here, the Digikey part ref is correct and the description mentions SOIC16WIDE. It's just that sneaky 3 that makes all the difference. The Farnell item description does not make it clear which version is the wide one, you need to go to the manufacturers data sheet for that.
 
#851
IL715 BOM error

Sorry for the error in the description. Initial plan was to use the narrow soic version and bom was created accordingly but then folks wanted option for similar types from other manufactures but these were only available in wide version from so design/bom was changed with new vendor part# but I possibly overlooked the description field containing Mfg part#.

Vendor part# is the reference. I would advise you check carefully before getting equivalent from elsewhere. Component images and description from Farnell can sometime be misleading.
 
#855
It is available in the updatetools "firmware programming" tab, click the CPLD/CPU drop down lists and you'll see them. The next pic is for CPLD but CPU works the same way.

1080_zps60af2ba7.jpg


Note: The CPU info box mentions the corrected XO selector is pin 1 but it should say pin 11. I'm away from home and cannot test myself.

Latest update tools are available here:
http://amanero.com/oemtool115.zip
 
#857
avian said:
Just wondering about the information posted here http://www.diyaudio.com/forums/vend...i2s-384khz-dsd-converter-171.html#post3606940 (post #1704).. I'm waiting on parts from digikey and the latest amanero board to arrive, and am wondering if this information is relevent? and will I need to remove some pins from the header on the S03 because I will be pairing it with the latest revision amanero?
Click to expand...

amanero said:
hello, the lines are in sequence D64 (F0) F1 F2 F3
They are open collectors and you can ground them when not used.
Click to expand...

No changes unless you wish to monitor the F0-F3 lines
 
#860
Jackal29a said:
It is available in the updatetools "firmware programming" tab, click the CPLD/CPU drop down lists and you'll see them. The next pic is for CPLD but CPU works the same way.

Note: The CPU info box mentions the corrected XO selector is pin 1 but it should say pin 11. I'm away from home and cannot test myself.
Click to expand...


If you flash
CPLD=1080
FIRMWARE=1080
Then Configuration Bits->Slave mode is ignored regardless of any pin 1 or 11 setting. Pin 6 remains as MCK output.
The result of this is confusing as concurrently the Amanero is OUTPUTTING MCK and the SO3 is INPUTTING MCK into the Amanero - both clocks get mixed together - but - the DAC plays (!) with plenty of crackling. So you waste an hour checking all the wrong things. Doh !

If you flash
CPLD=SLAVE2224
FIRMWARE=1080
Then Configuration Bits->Slave mode works as follows -
Pin fs Group Logic Level
11 44.1 LOW
11 48 HIGH
1 44.1 HIGH
1 48 LOW

You can use any combination - Pin 1 or Pin 11 or both (obviously you only need to enable the one you intend to use).

All the XOs I know of are OE=HIGH. From memory the old version of AKX302 Support.pdf may have X1 and X2 the wrong way round for the above select logic. I have overwritten the old AKX302 Support.pdf.
 
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