One channel good; one channel bad
I pulled out my F4 boards and put in these ZM Aleph J PCBs. Left channel sounds great; right channel has a DC offset minimum of 517 mV. I've only connected the left channel to speakers of course. Bias for both channels is about 430 mV, which I'll probably drop to about 375 whenever I get the DC offset problem sussed out.
Enjoy my fine photography!
The SE short has a tiny bit of red insulation on it--not a diode or anything.
I pulled out my F4 boards and put in these ZM Aleph J PCBs. Left channel sounds great; right channel has a DC offset minimum of 517 mV. I've only connected the left channel to speakers of course. Bias for both channels is about 430 mV, which I'll probably drop to about 375 whenever I get the DC offset problem sussed out.
Enjoy my fine photography!
The SE short has a tiny bit of red insulation on it--not a diode or anything.
positive offset means lower mosfet not open enough, asking for more ohms in input JFet drain (trimpot)
if you decrease Iq, fiddling with other trimpot, offset would also go down
write what you get
present Iq (430mV@0R27=1A59) is fine, if you can cool it
confirm that you have proper Ig through LTP (same reading at both channels across R13, expect something as 8V7)
if that is the case ( and you did your setting with inputs grounded, no load at output) , you can slightly increase R9 ; back up with TP1, increase R9 to 1K
if you decrease Iq, fiddling with other trimpot, offset would also go down
write what you get
present Iq (430mV@0R27=1A59) is fine, if you can cool it
confirm that you have proper Ig through LTP (same reading at both channels across R13, expect something as 8V7)
if that is the case ( and you did your setting with inputs grounded, no load at output) , you can slightly increase R9 ; back up with TP1, increase R9 to 1K
Attachments
DC offset was -592 mV, not positive as I originally described it.
8.5V across R13. 8.2V on the "good" channel.
Reduced bias to 1.37A (370mV). Reflowed solder on R9 and a couple of other connections. No change in DC offset, 580mV plus (trim pot ~middle value).
I guess the next step is to try a 1K resistor at R9 . . .
8.5V across R13. 8.2V on the "good" channel.
Reduced bias to 1.37A (370mV). Reflowed solder on R9 and a couple of other connections. No change in DC offset, 580mV plus (trim pot ~middle value).
I guess the next step is to try a 1K resistor at R9 . . .
Interesting. Asking for learning purposes, differing currents between J1 and J2 affects output stage, meaning offset/bias, hence poorly matched JFETs can nescessitate altering resistor values?
If so, what about widely varying Vgs between output devices? Say one MOSFET @ 3V9 and one @ 4V3?
Maybe stupid questions, but you know village idiots need to ask.
Regards,
Andy
If so, what about widely varying Vgs between output devices? Say one MOSFET @ 3V9 and one @ 4V3?
Maybe stupid questions, but you know village idiots need to ask.
Regards,
Andy
regarding ease of settings, same performance of both channels , it goes:
-first thing is having simillar currents through LTP in both channels - matter of small BC556 in CCS
-second thing is JFets matching
-third thing is mosfet matching
in praxis , only second thing important; only in case of Gremlins choosing mentioned parts from diametrically opposed ends of pool, you can expect difference in channels gain
and even then, exchange few parts between channels, and you're good
-first thing is having simillar currents through LTP in both channels - matter of small BC556 in CCS
-second thing is JFets matching
-third thing is mosfet matching
in praxis , only second thing important; only in case of Gremlins choosing mentioned parts from diametrically opposed ends of pool, you can expect difference in channels gain
and even then, exchange few parts between channels, and you're good
JFets, OK
matching mosfets ....... that was exactly mistake you make ...... this Aleph J is advertised as "no matching needed!! (except JFets)"
is it singing already?