Addressing John Curl's concerns on low noise designs

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Here is my input, John:
Toshiba is Japanese company. Looking at the attached picture can anybody say that they don't care of Beta?
 

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semantic game?

Wavebourn said:
It is not wrong; it is difficult to use comprehensive equations. But it is rewarding, if to do properly. Simplified approach is valid when topology and technology forgives such simplifications, but such a way you can't design something new and exciting.

As far as I know, no one advocates such a simplified approach. Making a circuit less sensitive for variables we have little control over, is not the same as simply ignoring these variables. I'm only saying that looking at a BJT as a VCCS AND considering Ib (for example) as a 'nuisance' may help towards better designs.

Also, I'm not saying that a perfectly flat beta is totally irrelevant. Of course it will improve performance. But a design that only works nice with hand selected devices from a lot of say 10000 pieces is not my cup of tea, to put it mildly.

The result will be always the same: nice looking devices, good measurements, but sound worse than what Edmond Stewart calls "flawed designs".
The only way to escape from the cage of topologies that allows you to omit variables hard to use in calculations, is the way when you have to face the reality as it is.......
[snip]

That's exactly what I'm doing: facing the reality as it is. For example, you can't buy a bunch of trannies with beta=100.0 or exactly the same Early effect, Cob etc.
BTW, perhaps you don't know it, but if there is one person who has escaped from the 'cage of topologies', then it's me.

As for your other reply, post #174, I got the impression that you simply refuses to understand my point of view, or is it just a silly semantic game?
Let's take my first point for example, the output of a pre-amp.
Of course, such output has some Ri (say 50 Ohms). And of course the output voltage depends (a little bit) on the load. But, normally we still call it a voltage source and certainly not a current source, just because of a non-zero Ri.

Following your reasoning, voltage sources don't exist, because Ri will never be zero. And what about current sources? They always exhibit a finite parallel impedance, so they are actually voltage sources, or they simply don't exist either? In that case all that is left are just 'sources'. 😀

Cheers,
Edmond.
 
MAC

Sebastiaan said:
Dear John,

A little bit of topic, Nice to see you use mac as well. But tell me is there any (besides eagle) design software for MAC? Unfortunately I still need to switch to Windblows for my audio designs, since there is hardly any software for the MAC.

with best regards,
Bas

Hi Bas,

Early versions of MicroCap run on a MAC. But I can't recommend this antique S/W. So, if you like it or not, you have to switch to 'windhoos'.
BTW, XP isn't that bad. Also, today's PCs are bloody fast, which you will really appreciate when running a simulation.
(I've a water cooled dual core CPU running at 3.6GHz)

Cheers,
Edmond.
 
Re: Re: minimum stage count

forr said:
Hi Edmond,
Some people are interested by CMCL :
http://www.diyaudio.com/forums/showthread.php?postid=1213768#post1213768
and following posts.
There were also some schematics of CMLC published in EWWW (Jager's hybrid amp, Marcel Van de Gevel's mosfet amp and one from you, I think).

Hi Forr,

I'm glad to hear that I'm not the only one who recognizes the virtues of a CMCL. In addition to your reference, there exists another thread about this topic, but where? It contains a description of a CMCL based on a opto coupler.
BTW, I think some people don't like my implementation of a CMCL because of 8 additional trannies for the full blown version (and 4 trannies for a 'light' version). But, apart from increased VAS gain and no VAS fighting, my latest version serves/simplifies a quadruple purpose:
1. CMCL (of course)
2. OPS voltage clamp
3. OPS current limiting
4. OPS Error correction
Not that bad for only 8 extra trannies, I would think. 😀

@Wavebourn
All these four thingies are new and complemented with a new implementation of NDFL (without nasty clipping behavior). So, regarding that 'cage of topologies', what are you talking about anyhow?

Cheers,
Edmond.
 
john curl said:
Ray, we run in different circles. If you have never been near any of my designs over the last 35 years, so be it.
Just this weekend, I received a request for an upgrade to a Levinson design that I made 34 years ago. That individual surprised me in even knowing about the upgrade, because I only did it once, and to my own personal unit.

You need to get out more John 😉

I know plenty of people who have purchased second hand Japanese audio equipment from the same vintage and later as your Mark Levinson and have refurbished it with new parts etc and they are now as happy as Larry 😉

Like someone else implied, who makes the best silicon ?? It's certainly not designed and made by audio gurus although the engineers responsible may have an interest and good understanding of audio applications.
 
Hi Edmond,

---I'm glad to hear that I'm not the only one who recognizes the virtues of a CMCL. In addition to your reference, there exists another thread about this topic, but where? It contains a description of a CMCL based on a opto coupler.---

I am not aware of another thread about CMCL and would be glad to read it. CMCL with an opto was in your EWWW article about biasing a Mosfet output stage.


---BTW, I think some people don't like my implementation of a CMCL because of 8 additional trannies for the full blown version (and 4 trannies for a 'light' version). But, apart from increased VAS gain and no VAS fighting, my latest version serves/simplifies a quadruple purpose:
1. CMCL (of course)
2. OPS voltage clamp
3. OPS current limiting
4. OPS Error correction
Not that bad for only 8 extra trannies, I would think.---

All desirable features I like. Any published schematics ?
 
serendipity

forr said:
Hi Edmond,
[snip]
All desirable features I like. Any published schematics ?

Hi Forr,

Not yet. I think it's better to build that thing first and then publish. Besides, I have to investigate the EC part into more detail. The funny thing is that even myself don't fully understand yet why and how it works. As a matter of fact, I stumbled upon this trick more or less by accident when playing with my simulator. A real serendipity.
To raise a corner of the veil, it's based on capacitive and positive feedback, roughly in the same way as has been done with the AD797 by means of Cn. But topologically, it's completely different. One more hint: it only works if TMC is applied as well (NOT TPC, as it will result in a disaster. 😀)

BTW, opposed to TMC, TPC is also incompatibly with NDFL. So, at least for me, TPC is a dead end.

As for the voltage clamp, look here: http://www.diyaudio.com/forums/showthread.php?postid=1797904#post1797904 and here: http://www.diyaudio.com/forums/showthread.php?postid=1801149#post1801149

For a very basic schematic of the new NDFL implementation look here: http://www.diyaudio.com/forums/showthread.php?postid=1776548#post1776548
The AD745 will be replaced by AD797 plus a separate output stage, so that the supply pins of the op-amp can be directly tied to +/-15V. I don't like to use these pins as signal outputs, simply because op-amps aren't specified for such applications, in particular with regard to (more?) noise. You never know in advance whether an op-amp is 'Alexander friendly' so to say.


Cheers,
Edmond.
 
JPV,
you may have misunderstood me, which most probably is not your fault.
I meant to say that available correct information, like yours, does not prevent widespread myths and misconceptions. This issue is not the only one.
A deep exploration of the P-N junction, the basis of almost every semiconductor, gives many answers, showing functional and casual relations.
The book explains well why the emitter -base voltage as a control element is the most usefull view and why the current control is not. The base current is a recombination and injection current essentially a defect current coming from second order effects.
 
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