I just realized I made a significant error in interpreting the AD768 noise specification above. Since the relevant output is IoutB, that one has full-scale output with all data pins at logic 0, not logic 1. So the noise spec is actually the best case, not the worst case. Very clever that they used the IoutB pin for the measurement eh? After all, its the untrimmed output, who knows what the INL/DNL is for it.
Hi Abraxalito 🙁
Since it is BCK is present as input, dac obviously working in stopped BCK mode? Without present BCK parallel Data bus cant be loaded?
So conversion takes on after LSB and last BCK cycle finished?
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LE has to be synced with BCK and it is external? As some Enabele pulse to 595 output buffers or so?
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Does MSB has to be inveted from say I2S data word?
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I am thinking to try this ancient dac 🙁
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(in almost all of these DACs datasheets graphical representation of inputs is missing...)
Since it is BCK is present as input, dac obviously working in stopped BCK mode? Without present BCK parallel Data bus cant be loaded?
So conversion takes on after LSB and last BCK cycle finished?
.
LE has to be synced with BCK and it is external? As some Enabele pulse to 595 output buffers or so?
.
Does MSB has to be inveted from say I2S data word?
.
I am thinking to try this ancient dac 🙁
.
(in almost all of these DACs datasheets graphical representation of inputs is missing...)
The AD768 does not have bit clock . It does not need it. It only needs one clock, the conversion clock.
Hi Zoran - you're talking as if this DAC has a serial input. But it doesn't, its a parallel input chip. As @rfbrw says it only has the one clock, the one that latches the parallel input into the DAC.
I have used 74HC164s in my parallel interface to it - they are simpler than 595s.
Yes, AD768 is offset binary, not twos complement like I2S.
I know that is parallel data input DAC that is because I am asking 🙂 I wrote "parallel data bus" not serial data...
That is what i asked for... So You just invert MSB to make DAC working?
I am saking this because in the datasheet was noted that is unipolar straight binary...
I persume that You interweene with I current injection or somehing as adjusting REFIN/REFOUT current?
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Thanks
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Can You tell us more about listeninig impressions please?
Actually the SCK determines individual bit parallel loading into the DAC. BUT that burst of BCKs followed with parallel data has to be in some period, some distance, that is LE or Fs time...
So LE can be Enable event long as BCK length, for the example buffer 16x register, prior to DAc data inputs?
I
But obviously DAC will not work without propper CLK related to parallel DATA input?
I didn't mention micro-controller?
But obviously DAC will not work without propper CLK related to parallel DATA input?