About the PLL

[hill]

Could anybody please help tell me how can i reduce phase noise when i using a pll circuit? I want to build a pll to suite the ferquency from 11MHz to 25MHz, how can i do this?

 

[Dave]

PLLs are tricky to design and very expensive.

I considered one for my next project but now I am working on a system using an Analog Devices Direct Digital Synthesis chip combined with a FIFO.

Take a look at my site -

http://www.geocities.com/d_broadhurst/index.html

 

[rfbrw]

Hill,
I'm not sure what you are want to do. Do you want a Pll circuit that sweeps or steps from 11Mhz to 25Mhz or a circuit that will lock a 25Mhz signal to a 11Mhz reference ? Either way, Philips Semiconductor have a 70page design guide for their 4046,7046 and 9046 HC/HCT series plls available by request at
http://www.philipslogic.com/products/hc/ . The PLL Design Guide request information is at the bottom of the page along with some design software. National Semiconductor www.natsemi.com
also have data on pll phase noise and though most of it refers to the GHz spectrum the general principles should still apply.
HTH ray.

 

[hill]

ray,

Aha, at facts I want to design a pll circuit which can sweeps from 11Mhz to 25Mhz with low phase jitter.
But i don't know how i can design a boardband vcxo with low jitter. I'd browse any website, i could not found the boardband vcxo yet. But i think the DDS technology is the best chioce.

hill

 

[rfbrw]

Can you explain why need such a wide range and do you actually need it to sweep from 11Mhz to 25Mhz or do you need a number of spot frequencies between 11Mhz and 25Mhz?

ray.

 

[hill]

Ray,

Because i want to use the circuit to suite all of the digital audio source. They'er HDTV(32k samping rang), CD(44.1k), MD(48k), DVD(96k)., the system clock of them will start from 8.192MHz to 24.576MHz. So i need the boardband oscillator, my idea is right?

hill

 

[Dave]

Hill,

You can't build a VCXO based PLL to lock to every frequency in that range.

You use two VCXOs. One is used to lock to frequencies which are a multiple of 44.1 KHz - 44.1, 88.2 etc. the other locks to multiples of 48 KHz - 48, 96, 192.

You need the appropriate dividers (to divide the output of the VCXOs to get to the lower sampling rates) and switching logic to switch between VCXOs and divider outputs.

You will probably want to use the 9046 for the phase comparator. It is a charge pump and is the most advanced one I know of. It does not suffer from something which I think is called backlash.

After that you need to get VCXOs custom cut to the exact frequency you need ($$$$.$$) - they should have a pull range around 400ppm.

Next you'll have to design the loop filter - the most critical part.

I gave up at this stage and started designing my FIFO based solution which is coming along quite nicely.

 

[rfbrw]

Hill,
The AD98xx approach will probably prove easier and more accurate given what you want to do. It woud also need fewer chips as the AD98xx chip would output the exact frequency you want under under the control of PIC or AVR micro. The only minus point I can see is if you want to lock to an external signal, for example the Fsync/Wordclock output of a CD player or DAT machine.
I would have to disagree with Dave on PLLs. The dividers are trivial and Vcxos are readily available where I am (UK). As with all analogue design trade-offs are involved but loop filters are not nearly as difficult as Dave seems to suggest.

ray.

 

[Dave]

rfbrw,

I realise the PLL filter is workable but I found trying to source VCXOs very, very difficult. In the end I decided on the DDS solution which I think will provide better performance. It would also be cheaper than the VCXOs.
I am using an AVR micro to control it.

Dave.

 

[rfbrw]

Dave,
Dont get me wrong I think the DDS approach is much better than using an analogue PLL. The only is that I could not find a method of locking to an external reference without using a VCXO, which is probably cheaper these days than a K-grade BB PCM63, or somehow digitizing the error signal and controlling the AD98xx
that way.

RAY

 

[hill]

RAY,

I have a question, if i using the DDS approach it means that i can use a 125MHz ref. clock for the AD9851 to get 8.192 or 11.2896 or 12.288 or 16.9344 or 18.432 or 24.576Mhz........... sine signal output from it, is it right?
In other hand, i want to use a FPGA as ref. counter, phase comparer & DDS control, is it a good idea? Will it down greade the system perfromance?

Hill

 

[rfbrw]

Hill,
From my understanding of the AD DDS chips, you need a narrow band filter for best performance. Reading through the AD9850 datasheet, it refers to a low pass filter with a cut off of 42Mhz with a reference of 125MHz. So if you go with the example filter of AD evaluation board you should have no problems generating the frequencies you need directly and this method will provide the cleanest clock. If you happen need more than one of the frequencies you referred to you can divide down using 74 series logic. Of course, if you happen to want 24.576 and 18.432 Mhz at the same time you will need two DDS chips. It will be a lot easier to control the DDS chip with something like an AVR or PIC microcontroller. Perhaps Dave who has alot more experience with DDS chips might add comment or two on this topic.

ray.

 

[hill]

RAY,

Thanks for you reply. I know what can i do with DDS.



Dave,

I could not reached your website,

http://www.geocities.com/d_broadhurst/index.html

maybe my ISP has filtered this IP, how can i see it? I really want to browse your website for reference. Can u help me?

Hill

 

[Unbeliever666]

Hi all!
I agree that the approach with the DDS seems superior, but, I was wondering about the jitter. A normal VCXO can have as low as 1ps of jitter. In the datasheet for the AD9850 it says that normal jitter is 80ps. That is about as much as the CS8414 has. In that case, why use AD9850?

/ Henrik

 

[Dave]

hill,

I tried my website - it seems to be working. Sometimes geocities switch it off because the traffic is too high.

rfbrw,

You should not need more than one particular frequency at any one time. Thus you will not need more than one DDS chip or any dividers. When the input sampling rate changes the micro controller just changes the output frequency of the DDS chip to match the new input sampling rate. The output frequency of the DDS chip can vary over a very wide range and in very small steps about 0.029Hz step size with a 125MHz reference clock.

The low pass filter defines the maximum frequency the output of the DDS can operate at. AD recommend this be no more than 33% of the reference clock frequency.

Unbeliever666,

Yes the AD9850 may have jitter higher than a good VCXO. But a DDS based solution should reject jitter coming into the DAC much better than a PLL and much much better than a CS8414.

Thus for a given level of input jitter the DDS approach should have the least amount of jitter at its output, in general.

Also the 80ps is the spec for the comparator built into the AD9850. It may be possible to realise lower jitter with an external comparator and good filtering.

 

[Unbeliever666]

Dave:
So if I use the DDS approach, control the freq with a microproc and reclock the i2s data with a FIFO, this should do the trick?
I probably should check almost empty/full flags of the FIFO to make shure that it operates perfectly?

Henrik

 

[hill]

Dave,

Could you pls recommended a chip for lower jitter than the built in one of AD9850.

 

[hill]

Henrik,

I recommend that you can use BCKO from CS8412/4 as the FIFO's write clock & divide down the output signal of DDS chip as the FIFO's read clock, so it can reduce depth of FIFO.
In the other hand, you can monitor the flags of FIFO to ensure the clock ferquency of DDS is right or not.

Hill

 

[Dave]

Unbeliever666,

Yes some how your going to have to monitor the FIFO flags to control the DDS chip frequency.

hill,

I am currently looking for a lower jitter solution than the internal comparator. I have not yet come to a solution.

 

[hill]

I think the different PECL can be.

Hill